Agilex™ 7 M-Series FPGA Network-on-Chip (NoC) User Guide

ID 768844
Date 8/05/2024
Public
Document Table of Contents

3.4.5. Connectivity Guidelines: NoC Initiators for HPS

The Hard Processor System Intel Agilex 7 / Agilex 9 FPGA IP contains the NoC initiator bridges for HPS. Connect all non-NoC interfaces of the HPS in accordance with the HPS IP user guidelines.

  • If you are using the Platform Designer connection flow, as NoC Design Flow Options describes, instantiate your NoC IP in Platform Designer. Connect the HPS AXI4 NoC manager interface on the Hard Processor System Intel Agilex 7 / Agilex 9 FPGA IP only to AXI4 NoC subordinate interfaces on External Memory Interfaces for HPS Intel FPGA IP. Do not connect the initiator bridges in the HPS IP to memory resources for fabric-facing AXI4 managers. After connecting AXI4 NoC manager and AXI4 NoC subordinate interfaces, click the Address Map tab to specify the base address for each connection. If an AXI4 NoC manager interface connects to multiple AXI4 NoC subordinate interfaces, ensure each connection has a unique starting address. You can click the Assign Base Addresses button to allow Platform Designer to assign addresses automatically.
  • If you are using the NoC Assignment Editor connection flow, as NoC Design Flow Options describes, instantiate your NoC IP in Platform Designer and leave the HPS AXI4 NoC manager interface unconnected. After running Quartus® Prime Analysis & Elaboration, you can use the NoC Assignment Editor to define connectivity and addressing to prepare your design for RTL simulation. Note that HPS designs only support design entry using Platform Designer. HPS designs do not support direct RTL instantiation.

For details on HPS EMIF IP, refer to refer to the Intel Agilex 7 Hard Processor System Component Reference Manual.