Agilex™ 7 M-Series FPGA Network-on-Chip (NoC) User Guide

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ID 768844
Date 9/30/2024
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Document Table of Contents
Document Table of Contents x
Answers to Top FAQs 1. Network-on-Chip (NoC) Overview 2. Hard Memory NoC in Agilex™ 7 M-Series FPGAs 3. NoC Design Flow in Quartus® Prime Pro Edition 4. NoC Real-time Performance Monitoring 5. Simulating NoC Designs 6. NoC Power Estimation 7. Hard Memory NoC IP Reference 8. Document Revision History of Agilex™ 7 M-Series FPGA Network-on-Chip (NoC) User Guide
1. Network-on-Chip (NoC) Overview x
1.1. Introduction to Agilex™ 7 M-Series FPGAs 1.2. Terminology for Intel Agilex® 7 M-Series FPGAs 1.3. General NoC Architecture and Applications
1.3. General NoC Architecture and Applications x
1.3.1. General NoC Architecture 1.3.2. Example NoC Applications
1.3.2. Example NoC Applications x
1.3.2.1. Parallel Computing NoC Application 1.3.2.2. SmartNIC NoC Application
2. Hard Memory NoC in Agilex™ 7 M-Series FPGAs x
2.1. High-Level Architecture 2.2. NoC Segments 2.3. NoC Switch and Link Detail 2.4. Fabric NoC 2.5. NoC Protocol Support 2.6. NoC Design Considerations
2.2. NoC Segments x
2.2.1. UIB Segments 2.2.2. GPIO-B Segments 2.2.3. GPIO-B and HPS Segment 2.2.4. SDM Segment 2.2.5. PLL and SSM Segment
2.5. NoC Protocol Support x
2.5.1. AXI4 Protocol Support 2.5.2. AXI4 Handshaking Support 2.5.3. Quality of Service (QoS) Support 2.5.4. Transaction Ordering Support 2.5.5. AXI4-Lite Protocol Support
2.6. NoC Design Considerations x
2.6.1. Determining the Number of NoC Targets 2.6.2. Determining the Number of NoC Initiators 2.6.3. Fabric NoC Considerations 2.6.4. Latency Considerations 2.6.5. Initiator and Target Bandwidth Considerations 2.6.6. Horizontal Bandwidth Considerations 2.6.7. GPIO-B Bypass Mode and Initiators
3. NoC Design Flow in Quartus® Prime Pro Edition x
3.1. Hard Memory NoC Design Flow Overview 3.2. Using NoC Example Designs 3.3. NoC Building Blocks 3.4. Connecting NoC IP 3.5. Making NoC Logical Assignments 3.6. Making NoC Physical Assignments Using Interface Planner 3.7. Compiling the NoC Design
3.1. Hard Memory NoC Design Flow Overview x
3.1.1. NoC Design Flow Options
3.3. NoC Building Blocks x
3.3.1. NoC Initiators for Hard Processor Systems 3.3.2. NoC Targets for Hard Processor Systems 3.3.3. NoC Initiators for Fabric AXI4 Managers 3.3.4. NoC Targets for Fabric AXI4 Managers 3.3.5. NoC Clock Control
3.4. Connecting NoC IP x
3.4.1. General NoC IP Connectivity Guidelines 3.4.2. Connectivity Guidelines: NoC Initiators for Fabric AXI4 Managers 3.4.3. Connectivity Guidelines: NoC Targets for Fabric AXI4 Managers 3.4.4. Connectivity Guidelines: NoC Clock Control 3.4.5. Connectivity Guidelines: NoC Initiators for HPS 3.4.6. Connectivity Guidelines: NoC Targets for HPS
3.4.1. General NoC IP Connectivity Guidelines x
3.4.1.1. Connecting NoC IP and Assigning Base Addresses in the Platform Designer Connection Flow 3.4.1.2. Connecting NoC IP and Assigning Base Addresses in the NoC Assignment Editor Connection Flow
3.5. Making NoC Logical Assignments x
3.5.1. Creating NoC Assignments for Compilation 3.5.2. Using the NoC Assignment Editor 3.5.3. Troubleshooting NoC Assignment Editor 3.5.4. NoC Connection and Addressing Examples
3.5.2. Using the NoC Assignment Editor x
3.5.2.1. Step 1: Make Group Assignments in the NoC Assignment Editor 3.5.2.2. Step 2: Make Connection Assignments in the NoC Assignment Editor 3.5.2.3. Step 3: Make Attribute Assignments in the NoC Assignment Editor 3.5.2.4. Step 4: Validate Logical NoC Assignments and Generate Simulation File
3.5.4. NoC Connection and Addressing Examples x
3.5.4.1. Example 1: External Memory Interface with 1 AXI4 Initiator and 1 AXI4-Lite Initiator 3.5.4.2. Example 2: Two External Memory Interfaces with One AXI4 Initiator and One AXI4-Lite Initiator 3.5.4.3. Example 3: One External Memory Interfaces with Two AXI4 Initiators and One AXI4-Lite Initiator 3.5.4.4. Example 4: Two High-Bandwidth Memory Pseudo-Channels with Two AXI4 Initiators (Crossbar) and Shared AXI4-Lite Initiator 3.5.4.5. Example 5: Hard Processor System with Two External Memory Interfaces
3.5.4.1. Example 1: External Memory Interface with 1 AXI4 Initiator and 1 AXI4-Lite Initiator x
3.5.4.1.1. Example 1: Platform Designer Connection Flow 3.5.4.1.2. Example 1: NoC Assignment Editor Connection Flow
3.5.4.2. Example 2: Two External Memory Interfaces with One AXI4 Initiator and One AXI4-Lite Initiator x
3.5.4.2.1. Example 2: Platform Designer Connection Flow 3.5.4.2.2. Example 2: NoC Assignment Editor Connection Flow
3.5.4.3. Example 3: One External Memory Interfaces with Two AXI4 Initiators and One AXI4-Lite Initiator x
3.5.4.3.1. Example 3: Platform Designer Connection Flow 3.5.4.3.2. Example 3: NoC Assignment Editor Connection Flow
3.5.4.4. Example 4: Two High-Bandwidth Memory Pseudo-Channels with Two AXI4 Initiators (Crossbar) and Shared AXI4-Lite Initiator x
3.5.4.4.1. Example 4: Platform Designer Connection Flow 3.5.4.4.2. Example 4: NoC Assignment Editor Connection Flow
3.5.4.5. Example 5: Hard Processor System with Two External Memory Interfaces x
3.5.4.5.1. Example 5: Platform Designer Connection Flow 3.5.4.5.2. Example 5: NoC Assignment Editor Connection Flow
3.6. Making NoC Physical Assignments Using Interface Planner x
3.6.1. Using Interface Planner 3.6.2. Recommended Placement Order for NoC Elements in Interface Planner 3.6.3. Hard Memory NoC Locations in Interface Planner 3.6.4. NoC Performance Reports in Interface Planner
3.7. Compiling the NoC Design x
3.7.1. Fitter NoC Reports 3.7.2. Viewing NoC Elements in Chip Planner
5. Simulating NoC Designs x
5.1. Generating a Simulation Registration Include File (Platform Designer Connection Flow) 5.2. Generating a Simulation Registration Include File (NoC Assignment Editor Connection Flow) 5.3. Contents of Simulation Registration Include File
6. NoC Power Estimation x
6.1. Using the Intel FPGA PTC to Estimate NoC Power
7. Hard Memory NoC IP Reference x
7.1. NoC Initiator Intel FPGA IP 7.2. NoC Clock Control Intel FPGA IP
7.1. NoC Initiator Intel FPGA IP x
7.1.1. NoC Initiator Intel FPGA IP Parameters 7.1.2. NoC Initiator Intel FPGA IP Interfaces
7.1.2. NoC Initiator Intel FPGA IP Interfaces x
7.1.2.1. NoC Initiator Intel FPGA IP AXI4/AXI4-Lite Interfaces 7.1.2.2. NoC Initiator AXI4 User Interface Signals 7.1.2.3. NoC Initiator Intel FPGA IP AXI4-Lite User Interface Signals 7.1.2.4. NoC Initiator Intel FPGA IP Clock and Reset Signals 7.1.2.5. NoC Initiator Intel FPGA IP Platform Designer-Only Signals
7.2. NoC Clock Control Intel FPGA IP x
7.2.1. NoC Clock Control Intel FPGA IP Parameters 7.2.2. NoC Clock Control Intel FPGA IP Interfaces 7.2.3. NoC Clock Control Intel FPGA IP Platform Designer-only Signals
Answers to Top FAQs
1. Network-on-Chip (NoC) Overview
2. Hard Memory NoC in Agilex™ 7 M-Series FPGAs
3. NoC Design Flow in Quartus® Prime Pro Edition
4. NoC Real-time Performance Monitoring
5. Simulating NoC Designs
6. NoC Power Estimation
7. Hard Memory NoC IP Reference
8. Document Revision History of Agilex™ 7 M-Series FPGA Network-on-Chip (NoC) User Guide

6.1. Using the Intel FPGA PTC to Estimate NoC Power

To estimate NoC power using the Intel FPGA PTC, follow these steps:

  1. To open the Intel FPGA PTC from the Intel Quartus Prime Pro Edition software, click Tools > Power and Thermal Calculator
  2. On the Main page, ensure that the selected device, device grade and transceiver grade match your device. NoC power estimation is only available for Agilex™ 7 M-Series FPGAs.
    Figure 56. Example Intel FPGA PTC NOC Page


  3. Under Total Dynamic Power, click NOC. The NOC page appears. Use any scrollbars along the right and bottom sides of the table to view additional rows or columns available for entry.

    The top portion of the Intel FPGA PTC shows results that calculate from the table at the bottom portion of the Intel FPGA PTC. These results include the NOC summary of total power, and the initiator and target utilization. The total power includes the power usage of the initiators and targets in the table, as well as the power usage of the hard memory NoC itself, and its supporting NoC PLL and NoC SSM. A breakdown of current draw per power rail also appears.

  4. Enter information about initiators and targets in your design in the table in the bottom portion of the Intel FPGA PTC. You can edit the Entity Name and Full Hierarchy Name fields. The report includes these two optional columns if you use them, and displays them in the PTC Module Manager.
  5. In the Block Type column, select whether the element on that row is an Initiator or a Target.
  6. In the Location column, select whether that initiator or target is associated with the hard memory NoC along the top edge of the die, or the hard memory NoC along the bottom edge of the die.
  7. In the # of Instances column, enter the number of initiator or target interface bridges for the element on this row. If you have multiple initiators (or multiple targets) that have the same clock frequency and bandwidth requirements, you can enter them on the same row. Otherwise, create separate rows for initiators or targets with different clock frequencies or different bandwidth requirements.
    Note: A single NoC Initiator Intel FPGA IP can contain multiple initiator interface bridges. Similarly, a target memory IP, such as the High Bandwidth Memory (HBM2E) Interface Agilex™ 7 FPGA IP, can contain multiple target interface bridges.
  8. For target elements only, specify details about the Memory Interface. In the Type column, select either HBM for HBM2e memory or DDR for external memory interfaces implemented in GPIO-B blocks. In the Clock Freq. (MHz) column, enter the clock frequency for these target interface bridges.
  9. For initiator elements only, use Initiator Clock Freq. (MHz) column to enter the clock frequency that the user interface for these initiators operates. If different initiators operate at different frequencies, you must specify each frequency on a separate row.
  10. For both initiator and target elements, use the Read and Write Bandwidth per Instance (GBps) columns to specify total read and write bandwidth for each element. If an initiator connects to multiple targets, enter the total of the bandwidth requirements for the connections from that initiator to all targets. Similarly, if a target connects multiple initiators, enter the total of the bandwidth requirements for the connections from all initiators to that target. This entry is for the read or write bandwidth per instance and expressed in GBps. The Utilization (%) displays the bandwidth utilization for each initiator or target. You must specify Initiator or target elements with different bandwidth requirements on separate rows.

    The following fields display the PTC results:

    • The Utilization (%) field displays the bandwidth utilization for each initiator or target.
    • Power (W) displays the power for the total initiators or targets specified on that row.
    • User Comment is a text field that you can edit that appears in the results report.

    This Intel FPGA PTC page only reflects the power usage of the NoC targets of IP, such as the High Bandwidth Memory (HMB2E) Interface Intel Agilex 7 FPGA IP. Estimate the power for the remainder of this IP elsewhere within the Intel FPGA PTC, for example on the HBM page.

  11. NoC initiators that have AXI4 read data widths greater than or equal to 512 bits use the fabric NoC to return read data via M20K memory blocks. For each initiator that has an AXI4 read data width greater than or equal to 512 bits, follow these steps to enter M20K memory block information:
    1. Click the RAM page.
    2. Create an entry in the table with the RAM Type set to M20K and # of Instances set to 16.
    3. Set the Vertical Network to Top or Bottom, based on the hard memory NoC that connects to the initiator. The Vertical Network Column specifies which column of M20K memory blocks the Fabric NoC is in. Make this column value unique for each initiator on the same edge of the device.
    4. Set the Data Width to 40 and the RAM Depth to 512.1 With the Vertical Network set to Top or Bottom, the RAM Mode automatically sets to Simple Dual Port. The parameters for Port A are based on the NoC operation that runs at 700 MHz in -1 and -2 speed grade devices, and at 500 MHz in -3 speed grade devices. The parameters for Port B are based on the AXI4 clock for the read interface of the initiator. The parameters for the Vertical Network Port set according to the expected traffic from the HBM2e or external memory.
Note: In addition to estimating power for the hard memory NoC and the optional fabric NoC extension, you also need to estimate power for any HBM2e Intel FPGA IP or External Memory Interface (EMIF) IP, as well as any other logic or IP in your design.
1 The is the width and depth of the M20Ks making up the fabric NoC.
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