Agilex™ 7 M-Series FPGA Network-on-Chip (NoC) User Guide

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ID 768844
Date 9/30/2024
Public
Document Table of Contents
Document Table of Contents x
Answers to Top FAQs 1. Network-on-Chip (NoC) Overview 2. Hard Memory NoC in Agilex™ 7 M-Series FPGAs 3. NoC Design Flow in Quartus® Prime Pro Edition 4. NoC Real-time Performance Monitoring 5. Simulating NoC Designs 6. NoC Power Estimation 7. Hard Memory NoC IP Reference 8. Document Revision History of Agilex™ 7 M-Series FPGA Network-on-Chip (NoC) User Guide
1. Network-on-Chip (NoC) Overview x
1.1. Introduction to Agilex™ 7 M-Series FPGAs 1.2. Terminology for Intel Agilex® 7 M-Series FPGAs 1.3. General NoC Architecture and Applications
1.3. General NoC Architecture and Applications x
1.3.1. General NoC Architecture 1.3.2. Example NoC Applications
1.3.2. Example NoC Applications x
1.3.2.1. Parallel Computing NoC Application 1.3.2.2. SmartNIC NoC Application
2. Hard Memory NoC in Agilex™ 7 M-Series FPGAs x
2.1. High-Level Architecture 2.2. NoC Segments 2.3. NoC Switch and Link Detail 2.4. Fabric NoC 2.5. NoC Protocol Support 2.6. NoC Design Considerations
2.2. NoC Segments x
2.2.1. UIB Segments 2.2.2. GPIO-B Segments 2.2.3. GPIO-B and HPS Segment 2.2.4. SDM Segment 2.2.5. PLL and SSM Segment
2.5. NoC Protocol Support x
2.5.1. AXI4 Protocol Support 2.5.2. AXI4 Handshaking Support 2.5.3. Quality of Service (QoS) Support 2.5.4. Transaction Ordering Support 2.5.5. AXI4-Lite Protocol Support
2.6. NoC Design Considerations x
2.6.1. Determining the Number of NoC Targets 2.6.2. Determining the Number of NoC Initiators 2.6.3. Fabric NoC Considerations 2.6.4. Latency Considerations 2.6.5. Initiator and Target Bandwidth Considerations 2.6.6. Horizontal Bandwidth Considerations 2.6.7. GPIO-B Bypass Mode and Initiators
3. NoC Design Flow in Quartus® Prime Pro Edition x
3.1. Hard Memory NoC Design Flow Overview 3.2. Using NoC Example Designs 3.3. NoC Building Blocks 3.4. Connecting NoC IP 3.5. Making NoC Logical Assignments 3.6. Making NoC Physical Assignments Using Interface Planner 3.7. Compiling the NoC Design
3.1. Hard Memory NoC Design Flow Overview x
3.1.1. NoC Design Flow Options
3.3. NoC Building Blocks x
3.3.1. NoC Initiators for Hard Processor Systems 3.3.2. NoC Targets for Hard Processor Systems 3.3.3. NoC Initiators for Fabric AXI4 Managers 3.3.4. NoC Targets for Fabric AXI4 Managers 3.3.5. NoC Clock Control
3.4. Connecting NoC IP x
3.4.1. General NoC IP Connectivity Guidelines 3.4.2. Connectivity Guidelines: NoC Initiators for Fabric AXI4 Managers 3.4.3. Connectivity Guidelines: NoC Targets for Fabric AXI4 Managers 3.4.4. Connectivity Guidelines: NoC Clock Control 3.4.5. Connectivity Guidelines: NoC Initiators for HPS 3.4.6. Connectivity Guidelines: NoC Targets for HPS
3.4.1. General NoC IP Connectivity Guidelines x
3.4.1.1. Connecting NoC IP and Assigning Base Addresses in the Platform Designer Connection Flow 3.4.1.2. Connecting NoC IP and Assigning Base Addresses in the NoC Assignment Editor Connection Flow
3.5. Making NoC Logical Assignments x
3.5.1. Creating NoC Assignments for Compilation 3.5.2. Using the NoC Assignment Editor 3.5.3. Troubleshooting NoC Assignment Editor 3.5.4. NoC Connection and Addressing Examples
3.5.2. Using the NoC Assignment Editor x
3.5.2.1. Step 1: Make Group Assignments in the NoC Assignment Editor 3.5.2.2. Step 2: Make Connection Assignments in the NoC Assignment Editor 3.5.2.3. Step 3: Make Attribute Assignments in the NoC Assignment Editor 3.5.2.4. Step 4: Validate Logical NoC Assignments and Generate Simulation File
3.5.4. NoC Connection and Addressing Examples x
3.5.4.1. Example 1: External Memory Interface with 1 AXI4 Initiator and 1 AXI4-Lite Initiator 3.5.4.2. Example 2: Two External Memory Interfaces with One AXI4 Initiator and One AXI4-Lite Initiator 3.5.4.3. Example 3: One External Memory Interfaces with Two AXI4 Initiators and One AXI4-Lite Initiator 3.5.4.4. Example 4: Two High-Bandwidth Memory Pseudo-Channels with Two AXI4 Initiators (Crossbar) and Shared AXI4-Lite Initiator 3.5.4.5. Example 5: Hard Processor System with Two External Memory Interfaces
3.5.4.1. Example 1: External Memory Interface with 1 AXI4 Initiator and 1 AXI4-Lite Initiator x
3.5.4.1.1. Example 1: Platform Designer Connection Flow 3.5.4.1.2. Example 1: NoC Assignment Editor Connection Flow
3.5.4.2. Example 2: Two External Memory Interfaces with One AXI4 Initiator and One AXI4-Lite Initiator x
3.5.4.2.1. Example 2: Platform Designer Connection Flow 3.5.4.2.2. Example 2: NoC Assignment Editor Connection Flow
3.5.4.3. Example 3: One External Memory Interfaces with Two AXI4 Initiators and One AXI4-Lite Initiator x
3.5.4.3.1. Example 3: Platform Designer Connection Flow 3.5.4.3.2. Example 3: NoC Assignment Editor Connection Flow
3.5.4.4. Example 4: Two High-Bandwidth Memory Pseudo-Channels with Two AXI4 Initiators (Crossbar) and Shared AXI4-Lite Initiator x
3.5.4.4.1. Example 4: Platform Designer Connection Flow 3.5.4.4.2. Example 4: NoC Assignment Editor Connection Flow
3.5.4.5. Example 5: Hard Processor System with Two External Memory Interfaces x
3.5.4.5.1. Example 5: Platform Designer Connection Flow 3.5.4.5.2. Example 5: NoC Assignment Editor Connection Flow
3.6. Making NoC Physical Assignments Using Interface Planner x
3.6.1. Using Interface Planner 3.6.2. Recommended Placement Order for NoC Elements in Interface Planner 3.6.3. Hard Memory NoC Locations in Interface Planner 3.6.4. NoC Performance Reports in Interface Planner
3.7. Compiling the NoC Design x
3.7.1. Fitter NoC Reports 3.7.2. Viewing NoC Elements in Chip Planner
5. Simulating NoC Designs x
5.1. Generating a Simulation Registration Include File (Platform Designer Connection Flow) 5.2. Generating a Simulation Registration Include File (NoC Assignment Editor Connection Flow) 5.3. Contents of Simulation Registration Include File
6. NoC Power Estimation x
6.1. Using the Intel FPGA PTC to Estimate NoC Power
7. Hard Memory NoC IP Reference x
7.1. NoC Initiator Intel FPGA IP 7.2. NoC Clock Control Intel FPGA IP
7.1. NoC Initiator Intel FPGA IP x
7.1.1. NoC Initiator Intel FPGA IP Parameters 7.1.2. NoC Initiator Intel FPGA IP Interfaces
7.1.2. NoC Initiator Intel FPGA IP Interfaces x
7.1.2.1. NoC Initiator Intel FPGA IP AXI4/AXI4-Lite Interfaces 7.1.2.2. NoC Initiator AXI4 User Interface Signals 7.1.2.3. NoC Initiator Intel FPGA IP AXI4-Lite User Interface Signals 7.1.2.4. NoC Initiator Intel FPGA IP Clock and Reset Signals 7.1.2.5. NoC Initiator Intel FPGA IP Platform Designer-Only Signals
7.2. NoC Clock Control Intel FPGA IP x
7.2.1. NoC Clock Control Intel FPGA IP Parameters 7.2.2. NoC Clock Control Intel FPGA IP Interfaces 7.2.3. NoC Clock Control Intel FPGA IP Platform Designer-only Signals
Answers to Top FAQs
1. Network-on-Chip (NoC) Overview
2. Hard Memory NoC in Agilex™ 7 M-Series FPGAs
3. NoC Design Flow in Quartus® Prime Pro Edition
4. NoC Real-time Performance Monitoring
5. Simulating NoC Designs
6. NoC Power Estimation
7. Hard Memory NoC IP Reference
8. Document Revision History of Agilex™ 7 M-Series FPGA Network-on-Chip (NoC) User Guide

2.6.3. Fabric NoC Considerations

If you configure the NoC Initiator Intel FPGA IP with an AXI4 read data width of 512 or 576 bits, the IP implements the fabric NoC feature.

When you use this configuration, instead of delivering read data directly to the initiator read port, read data is written to a column of M20K memory blocks below the NoC initiator, as Figure 11. NoC Initiators With and Without Fabric NoC shows.

This configuration is ideal for applications that rely on high sequential read throughput. Usage of the fabric NoC feature for read data reduces pressure on fabric routing resources near the NoC initiator along the edge of the die.

Additionally, if you configure the NoC Initiator Intel FPGA IP with an AXI4 write data width of 512 or 576 bits, you can choose to implement the IP with a separate clock for the 256-bit wide initiator hardware. That clock can run as fast as 660 MHz for -1 speed grades, 630 MHz for -2 speed grades, and 450 MHz for -3 speed grade devices. With this option you can achieve up to 90% of sustained HBM2e write throughput. These 512-bit interfaces only support transactions that transfer multiples of 64 bytes, and target addresses that are aligned on 64-byte boundaries.

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