Agilex™ 7 M-Series FPGA Network-on-Chip (NoC) User Guide

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ID 768844
Date 9/30/2024
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Document Table of Contents
Document Table of Contents x
Answers to Top FAQs 1. Network-on-Chip (NoC) Overview 2. Hard Memory NoC in Agilex™ 7 M-Series FPGAs 3. NoC Design Flow in Quartus® Prime Pro Edition 4. NoC Real-time Performance Monitoring 5. Simulating NoC Designs 6. NoC Power Estimation 7. Hard Memory NoC IP Reference 8. Document Revision History of Agilex™ 7 M-Series FPGA Network-on-Chip (NoC) User Guide
1. Network-on-Chip (NoC) Overview x
1.1. Introduction to Agilex™ 7 M-Series FPGAs 1.2. Terminology for Intel Agilex® 7 M-Series FPGAs 1.3. General NoC Architecture and Applications
1.3. General NoC Architecture and Applications x
1.3.1. General NoC Architecture 1.3.2. Example NoC Applications
1.3.2. Example NoC Applications x
1.3.2.1. Parallel Computing NoC Application 1.3.2.2. SmartNIC NoC Application
2. Hard Memory NoC in Agilex™ 7 M-Series FPGAs x
2.1. High-Level Architecture 2.2. NoC Segments 2.3. NoC Switch and Link Detail 2.4. Fabric NoC 2.5. NoC Protocol Support 2.6. NoC Design Considerations
2.2. NoC Segments x
2.2.1. UIB Segments 2.2.2. GPIO-B Segments 2.2.3. GPIO-B and HPS Segment 2.2.4. SDM Segment 2.2.5. PLL and SSM Segment
2.5. NoC Protocol Support x
2.5.1. AXI4 Protocol Support 2.5.2. AXI4 Handshaking Support 2.5.3. Quality of Service (QoS) Support 2.5.4. Transaction Ordering Support 2.5.5. AXI4-Lite Protocol Support
2.6. NoC Design Considerations x
2.6.1. Determining the Number of NoC Targets 2.6.2. Determining the Number of NoC Initiators 2.6.3. Fabric NoC Considerations 2.6.4. Latency Considerations 2.6.5. Initiator and Target Bandwidth Considerations 2.6.6. Horizontal Bandwidth Considerations 2.6.7. GPIO-B Bypass Mode and Initiators
3. NoC Design Flow in Quartus® Prime Pro Edition x
3.1. Hard Memory NoC Design Flow Overview 3.2. Using NoC Example Designs 3.3. NoC Building Blocks 3.4. Connecting NoC IP 3.5. Making NoC Logical Assignments 3.6. Making NoC Physical Assignments Using Interface Planner 3.7. Compiling the NoC Design
3.1. Hard Memory NoC Design Flow Overview x
3.1.1. NoC Design Flow Options
3.3. NoC Building Blocks x
3.3.1. NoC Initiators for Hard Processor Systems 3.3.2. NoC Targets for Hard Processor Systems 3.3.3. NoC Initiators for Fabric AXI4 Managers 3.3.4. NoC Targets for Fabric AXI4 Managers 3.3.5. NoC Clock Control
3.4. Connecting NoC IP x
3.4.1. General NoC IP Connectivity Guidelines 3.4.2. Connectivity Guidelines: NoC Initiators for Fabric AXI4 Managers 3.4.3. Connectivity Guidelines: NoC Targets for Fabric AXI4 Managers 3.4.4. Connectivity Guidelines: NoC Clock Control 3.4.5. Connectivity Guidelines: NoC Initiators for HPS 3.4.6. Connectivity Guidelines: NoC Targets for HPS
3.4.1. General NoC IP Connectivity Guidelines x
3.4.1.1. Connecting NoC IP and Assigning Base Addresses in the Platform Designer Connection Flow 3.4.1.2. Connecting NoC IP and Assigning Base Addresses in the NoC Assignment Editor Connection Flow
3.5. Making NoC Logical Assignments x
3.5.1. Creating NoC Assignments for Compilation 3.5.2. Using the NoC Assignment Editor 3.5.3. Troubleshooting NoC Assignment Editor 3.5.4. NoC Connection and Addressing Examples
3.5.2. Using the NoC Assignment Editor x
3.5.2.1. Step 1: Make Group Assignments in the NoC Assignment Editor 3.5.2.2. Step 2: Make Connection Assignments in the NoC Assignment Editor 3.5.2.3. Step 3: Make Attribute Assignments in the NoC Assignment Editor 3.5.2.4. Step 4: Validate Logical NoC Assignments and Generate Simulation File
3.5.4. NoC Connection and Addressing Examples x
3.5.4.1. Example 1: External Memory Interface with 1 AXI4 Initiator and 1 AXI4-Lite Initiator 3.5.4.2. Example 2: Two External Memory Interfaces with One AXI4 Initiator and One AXI4-Lite Initiator 3.5.4.3. Example 3: One External Memory Interfaces with Two AXI4 Initiators and One AXI4-Lite Initiator 3.5.4.4. Example 4: Two High-Bandwidth Memory Pseudo-Channels with Two AXI4 Initiators (Crossbar) and Shared AXI4-Lite Initiator 3.5.4.5. Example 5: Hard Processor System with Two External Memory Interfaces
3.5.4.1. Example 1: External Memory Interface with 1 AXI4 Initiator and 1 AXI4-Lite Initiator x
3.5.4.1.1. Example 1: Platform Designer Connection Flow 3.5.4.1.2. Example 1: NoC Assignment Editor Connection Flow
3.5.4.2. Example 2: Two External Memory Interfaces with One AXI4 Initiator and One AXI4-Lite Initiator x
3.5.4.2.1. Example 2: Platform Designer Connection Flow 3.5.4.2.2. Example 2: NoC Assignment Editor Connection Flow
3.5.4.3. Example 3: One External Memory Interfaces with Two AXI4 Initiators and One AXI4-Lite Initiator x
3.5.4.3.1. Example 3: Platform Designer Connection Flow 3.5.4.3.2. Example 3: NoC Assignment Editor Connection Flow
3.5.4.4. Example 4: Two High-Bandwidth Memory Pseudo-Channels with Two AXI4 Initiators (Crossbar) and Shared AXI4-Lite Initiator x
3.5.4.4.1. Example 4: Platform Designer Connection Flow 3.5.4.4.2. Example 4: NoC Assignment Editor Connection Flow
3.5.4.5. Example 5: Hard Processor System with Two External Memory Interfaces x
3.5.4.5.1. Example 5: Platform Designer Connection Flow 3.5.4.5.2. Example 5: NoC Assignment Editor Connection Flow
3.6. Making NoC Physical Assignments Using Interface Planner x
3.6.1. Using Interface Planner 3.6.2. Recommended Placement Order for NoC Elements in Interface Planner 3.6.3. Hard Memory NoC Locations in Interface Planner 3.6.4. NoC Performance Reports in Interface Planner
3.7. Compiling the NoC Design x
3.7.1. Fitter NoC Reports 3.7.2. Viewing NoC Elements in Chip Planner
5. Simulating NoC Designs x
5.1. Generating a Simulation Registration Include File (Platform Designer Connection Flow) 5.2. Generating a Simulation Registration Include File (NoC Assignment Editor Connection Flow) 5.3. Contents of Simulation Registration Include File
6. NoC Power Estimation x
6.1. Using the Intel FPGA PTC to Estimate NoC Power
7. Hard Memory NoC IP Reference x
7.1. NoC Initiator Intel FPGA IP 7.2. NoC Clock Control Intel FPGA IP
7.1. NoC Initiator Intel FPGA IP x
7.1.1. NoC Initiator Intel FPGA IP Parameters 7.1.2. NoC Initiator Intel FPGA IP Interfaces
7.1.2. NoC Initiator Intel FPGA IP Interfaces x
7.1.2.1. NoC Initiator Intel FPGA IP AXI4/AXI4-Lite Interfaces 7.1.2.2. NoC Initiator AXI4 User Interface Signals 7.1.2.3. NoC Initiator Intel FPGA IP AXI4-Lite User Interface Signals 7.1.2.4. NoC Initiator Intel FPGA IP Clock and Reset Signals 7.1.2.5. NoC Initiator Intel FPGA IP Platform Designer-Only Signals
7.2. NoC Clock Control Intel FPGA IP x
7.2.1. NoC Clock Control Intel FPGA IP Parameters 7.2.2. NoC Clock Control Intel FPGA IP Interfaces 7.2.3. NoC Clock Control Intel FPGA IP Platform Designer-only Signals
Answers to Top FAQs
1. Network-on-Chip (NoC) Overview
2. Hard Memory NoC in Agilex™ 7 M-Series FPGAs
3. NoC Design Flow in Quartus® Prime Pro Edition
4. NoC Real-time Performance Monitoring
5. Simulating NoC Designs
6. NoC Power Estimation
7. Hard Memory NoC IP Reference
8. Document Revision History of Agilex™ 7 M-Series FPGA Network-on-Chip (NoC) User Guide

3.5.2.3. Step 3: Make Attribute Assignments in the NoC Assignment Editor

This step describes how to create attribute assignments on connections between initiators and targets using the NoC Assignment Editor. If your design uses the Platform Designer connection flow, as NoC Design Flow Options describes, you create address map assignments in Platform Designer. The design .qip file stores those assignments that appear automatically in the NoC Assignment Editor as read-only assignments. You must make any changes to these assignments only in Platform Designer.

If your design uses the Platform Designer connection flow, as NoC Design Flow Options describes, and you have not made group assignments for your NoC elements, the Attributes tab displays an <Ungrouped> subtab. The <Ungrouped> subtab shows attributes such as base addresses that you defined in Platform Designer, but whose elements you have not assigned to a NoC group. Before continuing with attribute assignments, click the Group tab and make group assignments for all NoC elements, as Step 1: Make Group Assignments in the NoC Assignment Editor describes.

  1. Complete the Group and Connection tab assignments before starting the Attribute tab assignments
  2. To create assignments for address mapping and bandwidth requirements for each connection, click the Attributes tab. The Attributes tab includes a subtab for each group that you specify on the Group tab. Each subtab lists each initiator to target connection.
Table 7.  Attributes Tab Options
Option Description
Base Address Enter the hexadecimal base address for each initiator-target connection. The set of targets that connect to an initiator is a memory-mapped space using physical addresses to define how the initiator reaches each target. Defining a connection between an initiator and a target and setting the base address of that connection creates a logical address space that is visible from the initiator's perspective.
Read Bandwidth Specify the steady-state required read bandwidth (in GB/s) for each initiator to target connection. The default setting is 0 GB/s.
Write Bandwidth Specify the steady-state required write bandwidth (in GB/s) for each initiator to target connection. The default setting is 0 GB/s.
Read Transaction Size Specify the average read transaction size (in bytes) for each initiator to target connection. Valid sizes are 32, 64, 128, 256, 512, 1024, 2048, or 4096. The default setting is 64.
Write Transaction Size Specify the average write transaction size (in bytes) for each initiator to target connection. Valid sizes are 32, 64, 128, 256, 512, 1024, 2048, or 4096. The default setting is 64.

Figure 24. NoC Assignment Editor Attributes Tab shows an example Attributes tab in the NoC Assignment Editor with the base addresses assigned for individual initiator-target connections.

Figure 24. NoC Assignment Editor Attributes Tab


Note: Use the right-side scrollbar to view additional initiator-target connects below. Use the bottom scrollbar to view additional columns to the right for assigning read and write bandwidth requirements.

If an initiator connects to multiple targets, select base addresses to avoid address range overlaps. For HBM2e memory, the minimum address span is 1 GB and you must align base addresses to 1 GB boundaries. For external memory interfaces, the minimum address span is 4 GB and you must align base addresses to 4 GB boundaries. For example, if an initiator connects to both HBM2e memory and DDR5 memory, you might select the base address for the HBM2e memory as 0x00000000, and the base address for the DDR5 memory as 0x40000000, assuming a 16GB HBM2e memory space. You can click the Assign Base Addresses button to allow Platform Designer to assign addresses automatically.

Read and write bandwidth is based on the traffic that you anticipate your system places on each initiator-target connection. You must account for the physical limits of the hard memory NoC, including initiator data widths and frequencies, and high-bandwidth memory or external memory interface limitations. Additionally, consider whether you need to limit traffic on certain connections to avoid overloading the horizontal bandwidth limits of the hard memory NoC. Since the hard memory NoC breaks down transactions into 512-bit (64-byte) packets, using a smaller transaction size of 32 bytes can result in inefficient usage of the hard memory NoC.

The NOC Performance Report estimates whether you can meet these performance targets. This report is available during interactive placement in the Interface Planner. In Interface Planner, results are based on estimated clock frequencies. After compilation, the Compilation Report also includes this report but is based on actual clock frequencies. For details, refer to Fitter NoC Reports. Additionally, the Power and Thermal Calculator (PTC) estimates power based on the bandwidth performance targets. Leaving the bandwidth requirements as the default (0 GB/s for both read and write traffic) can result in inaccurate performance reporting and power estimation.

The following shows the equivalent .qsf assignments for specifying the base address, bandwidth requirements, and transaction sizes. Base addresses are in hexadecimal format and do not require a leading 0x. Read and write bandwidth requirements are numeric values in GB/s. Read and write transaction sizes are in bytes. 

set_instance_assignment -name NOC_TARGET_BASE_ADDRESS <address> \
   -from <hierarchical initiator path name> \
   -to <hierarchical target path name>
set_instance_assignment -name NOC_READ_BANDWIDTH \
   <read bandwidth requirement> -from <hierarchical initiator path name> \
   -to <hierarchical target path name>
set_instance_assignment -name NOC_WRITE_BANDWIDTH \
   <write bandwidth requirement> -from <hierarchical initiator path name>\
   -to <hierarchical target path name>
set_instance_assignment -name NOC_READ_TRANSACTION_SIZE \
   <read transaction size> -from \
   <hierarchical initiator path name> -to \
   <hierarchical target path name>
set_instance_assignment -name NOC_WRITE_TRANSACTION_SIZE \
   <write transaction size> -from \
   <hierarchical initiator path name> -to \
   <hierarchical target path name>
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