Agilex™ 7 M-Series FPGA Network-on-Chip (NoC) User Guide

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ID 768844
Date 9/30/2024
Public
Document Table of Contents
Document Table of Contents x
Answers to Top FAQs 1. Network-on-Chip (NoC) Overview 2. Hard Memory NoC in Agilex™ 7 M-Series FPGAs 3. NoC Design Flow in Quartus® Prime Pro Edition 4. NoC Real-time Performance Monitoring 5. Simulating NoC Designs 6. NoC Power Estimation 7. Hard Memory NoC IP Reference 8. Document Revision History of Agilex™ 7 M-Series FPGA Network-on-Chip (NoC) User Guide
1. Network-on-Chip (NoC) Overview x
1.1. Introduction to Agilex™ 7 M-Series FPGAs 1.2. Terminology for Intel Agilex® 7 M-Series FPGAs 1.3. General NoC Architecture and Applications
1.3. General NoC Architecture and Applications x
1.3.1. General NoC Architecture 1.3.2. Example NoC Applications
1.3.2. Example NoC Applications x
1.3.2.1. Parallel Computing NoC Application 1.3.2.2. SmartNIC NoC Application
2. Hard Memory NoC in Agilex™ 7 M-Series FPGAs x
2.1. High-Level Architecture 2.2. NoC Segments 2.3. NoC Switch and Link Detail 2.4. Fabric NoC 2.5. NoC Protocol Support 2.6. NoC Design Considerations
2.2. NoC Segments x
2.2.1. UIB Segments 2.2.2. GPIO-B Segments 2.2.3. GPIO-B and HPS Segment 2.2.4. SDM Segment 2.2.5. PLL and SSM Segment
2.5. NoC Protocol Support x
2.5.1. AXI4 Protocol Support 2.5.2. AXI4 Handshaking Support 2.5.3. Quality of Service (QoS) Support 2.5.4. Transaction Ordering Support 2.5.5. AXI4-Lite Protocol Support
2.6. NoC Design Considerations x
2.6.1. Determining the Number of NoC Targets 2.6.2. Determining the Number of NoC Initiators 2.6.3. Fabric NoC Considerations 2.6.4. Latency Considerations 2.6.5. Initiator and Target Bandwidth Considerations 2.6.6. Horizontal Bandwidth Considerations 2.6.7. GPIO-B Bypass Mode and Initiators
3. NoC Design Flow in Quartus® Prime Pro Edition x
3.1. Hard Memory NoC Design Flow Overview 3.2. Using NoC Example Designs 3.3. NoC Building Blocks 3.4. Connecting NoC IP 3.5. Making NoC Logical Assignments 3.6. Making NoC Physical Assignments Using Interface Planner 3.7. Compiling the NoC Design
3.1. Hard Memory NoC Design Flow Overview x
3.1.1. NoC Design Flow Options
3.3. NoC Building Blocks x
3.3.1. NoC Initiators for Hard Processor Systems 3.3.2. NoC Targets for Hard Processor Systems 3.3.3. NoC Initiators for Fabric AXI4 Managers 3.3.4. NoC Targets for Fabric AXI4 Managers 3.3.5. NoC Clock Control
3.4. Connecting NoC IP x
3.4.1. General NoC IP Connectivity Guidelines 3.4.2. Connectivity Guidelines: NoC Initiators for Fabric AXI4 Managers 3.4.3. Connectivity Guidelines: NoC Targets for Fabric AXI4 Managers 3.4.4. Connectivity Guidelines: NoC Clock Control 3.4.5. Connectivity Guidelines: NoC Initiators for HPS 3.4.6. Connectivity Guidelines: NoC Targets for HPS
3.4.1. General NoC IP Connectivity Guidelines x
3.4.1.1. Connecting NoC IP and Assigning Base Addresses in the Platform Designer Connection Flow 3.4.1.2. Connecting NoC IP and Assigning Base Addresses in the NoC Assignment Editor Connection Flow
3.5. Making NoC Logical Assignments x
3.5.1. Creating NoC Assignments for Compilation 3.5.2. Using the NoC Assignment Editor 3.5.3. Troubleshooting NoC Assignment Editor 3.5.4. NoC Connection and Addressing Examples
3.5.2. Using the NoC Assignment Editor x
3.5.2.1. Step 1: Make Group Assignments in the NoC Assignment Editor 3.5.2.2. Step 2: Make Connection Assignments in the NoC Assignment Editor 3.5.2.3. Step 3: Make Attribute Assignments in the NoC Assignment Editor 3.5.2.4. Step 4: Validate Logical NoC Assignments and Generate Simulation File
3.5.4. NoC Connection and Addressing Examples x
3.5.4.1. Example 1: External Memory Interface with 1 AXI4 Initiator and 1 AXI4-Lite Initiator 3.5.4.2. Example 2: Two External Memory Interfaces with One AXI4 Initiator and One AXI4-Lite Initiator 3.5.4.3. Example 3: One External Memory Interfaces with Two AXI4 Initiators and One AXI4-Lite Initiator 3.5.4.4. Example 4: Two High-Bandwidth Memory Pseudo-Channels with Two AXI4 Initiators (Crossbar) and Shared AXI4-Lite Initiator 3.5.4.5. Example 5: Hard Processor System with Two External Memory Interfaces
3.5.4.1. Example 1: External Memory Interface with 1 AXI4 Initiator and 1 AXI4-Lite Initiator x
3.5.4.1.1. Example 1: Platform Designer Connection Flow 3.5.4.1.2. Example 1: NoC Assignment Editor Connection Flow
3.5.4.2. Example 2: Two External Memory Interfaces with One AXI4 Initiator and One AXI4-Lite Initiator x
3.5.4.2.1. Example 2: Platform Designer Connection Flow 3.5.4.2.2. Example 2: NoC Assignment Editor Connection Flow
3.5.4.3. Example 3: One External Memory Interfaces with Two AXI4 Initiators and One AXI4-Lite Initiator x
3.5.4.3.1. Example 3: Platform Designer Connection Flow 3.5.4.3.2. Example 3: NoC Assignment Editor Connection Flow
3.5.4.4. Example 4: Two High-Bandwidth Memory Pseudo-Channels with Two AXI4 Initiators (Crossbar) and Shared AXI4-Lite Initiator x
3.5.4.4.1. Example 4: Platform Designer Connection Flow 3.5.4.4.2. Example 4: NoC Assignment Editor Connection Flow
3.5.4.5. Example 5: Hard Processor System with Two External Memory Interfaces x
3.5.4.5.1. Example 5: Platform Designer Connection Flow 3.5.4.5.2. Example 5: NoC Assignment Editor Connection Flow
3.6. Making NoC Physical Assignments Using Interface Planner x
3.6.1. Using Interface Planner 3.6.2. Recommended Placement Order for NoC Elements in Interface Planner 3.6.3. Hard Memory NoC Locations in Interface Planner 3.6.4. NoC Performance Reports in Interface Planner
3.7. Compiling the NoC Design x
3.7.1. Fitter NoC Reports 3.7.2. Viewing NoC Elements in Chip Planner
5. Simulating NoC Designs x
5.1. Generating a Simulation Registration Include File (Platform Designer Connection Flow) 5.2. Generating a Simulation Registration Include File (NoC Assignment Editor Connection Flow) 5.3. Contents of Simulation Registration Include File
6. NoC Power Estimation x
6.1. Using the Intel FPGA PTC to Estimate NoC Power
7. Hard Memory NoC IP Reference x
7.1. NoC Initiator Intel FPGA IP 7.2. NoC Clock Control Intel FPGA IP
7.1. NoC Initiator Intel FPGA IP x
7.1.1. NoC Initiator Intel FPGA IP Parameters 7.1.2. NoC Initiator Intel FPGA IP Interfaces
7.1.2. NoC Initiator Intel FPGA IP Interfaces x
7.1.2.1. NoC Initiator Intel FPGA IP AXI4/AXI4-Lite Interfaces 7.1.2.2. NoC Initiator AXI4 User Interface Signals 7.1.2.3. NoC Initiator Intel FPGA IP AXI4-Lite User Interface Signals 7.1.2.4. NoC Initiator Intel FPGA IP Clock and Reset Signals 7.1.2.5. NoC Initiator Intel FPGA IP Platform Designer-Only Signals
7.2. NoC Clock Control Intel FPGA IP x
7.2.1. NoC Clock Control Intel FPGA IP Parameters 7.2.2. NoC Clock Control Intel FPGA IP Interfaces 7.2.3. NoC Clock Control Intel FPGA IP Platform Designer-only Signals
Answers to Top FAQs
1. Network-on-Chip (NoC) Overview
2. Hard Memory NoC in Agilex™ 7 M-Series FPGAs
3. NoC Design Flow in Quartus® Prime Pro Edition
4. NoC Real-time Performance Monitoring
5. Simulating NoC Designs
6. NoC Power Estimation
7. Hard Memory NoC IP Reference
8. Document Revision History of Agilex™ 7 M-Series FPGA Network-on-Chip (NoC) User Guide

8. Document Revision History of Agilex™ 7 M-Series FPGA Network-on-Chip (NoC) User Guide

Document Version Quartus® Prime Version Changes
2024.09.30 24.3
  • Updated Making NoC Physical Assignments Using Interface Planner topic for visualization of links and switches.
  • Updated Recommended Placement Order for NoC Elements in Interface Planner topic for visualization of links and switches.
  • Updated NoC Performance Reports in Interface Planner topic for Show NoC Congestion and visualization of the horizontal link congestion.
  • Added note to NoC Initiators for Fabric AXI4 Managers about verifying assignments with hierarchical names within the IP.
  • Added note to NoC Initiator Intel FPGA IP Parameters topic about verifying assignments with hierarchical names within the IP.
  • Revised Using Interface Planner step 8.
  • Updated Hard Memory NoC Locations in Interface Planner for latest locations.
2024.08.05 24.2
  • Showed user inaccessible AXI4 Lite targets in NoC UIB Segment diagram.
  • Revised signal direction in NoC Initiators With and Without Fabric NoC diagram.
  • Added notations about AXI4 Lite user non-accessible signals to Hard Memory NoC Locations in Interface Planner topic.
  • Revised horizontal link allocation diagrams in Horizontal Bandwidth Considerations topic.
2023.12.04 23.4
  • Updated Terminology for Intel Agilex® 7 M-Series FPGAs topic.
  • Added initiator and target numbering to diagrams in Horizontal Bandwidth Considerations topic.
  • Added Troubleshooting NoC Assignment Editor topic.
  • Updated screenshot in Compiling the NoC Design topic for latest Compilation Dashboard.
  • Added links to AN 1003: Multi Memory IP System Resource Planning for Agilex™ 7 M-Series FPGAs and other cross referencing enhancements throughout.
2023.10.12 23.3
  • Removed footnote indicting that the current version of software restricts device support for Agilex™ 7 M-series FPGAs and SoCs.
  • Updated Using NoC Example Designs topic to mention default read and write bandwidth settings.
  • Updated NoC Clock Control topic to mention AXI4 Lite targets in the High Bandwidth Memory (HBM2e) Interface Intel Agilex 7 FPGA IP and the External Memory Interfaces (EMIF) IP.
  • Revised Connecting NoC IP and Assigning Base Addresses in the Platform Designer Connection Flow topic to mention HPS AXI4.
  • Revised Connecting NoC IP and Assigning Base Addresses in the NoC Assignment Editor Connection Flow topic to mention HPS AXI4.
  • Revised Connectivity Guidelines: NoC Initiators for Fabric AXI4 Managers topic to mention Assign Base Addresses function.
  • Revised Connectivity Guidelines: NoC Targets for Fabric AXI4 Managers topic to mention Assign Base Addresses function.
  • Revised Connectivity Guidelines: NoC Clock Control topic to mention Assign Base Addresses function.
  • Revised Connectivity Guidelines: NoC Initiators for HPS topic to mention Assign Base Addresses function.
  • Revised Connectivity Guidelines: NoC Targets for HPS topic to mention Assign Base Addresses function.
  • Revised Step 2: Make Connection Assignments in the NoC Assignment Editor topic to describe the <Ungrouped> subtab.
  • Revised Step 3: Make Attribute Assignments in the NoC Assignment Editor topic to mention the <Ungrouped> subtab and Assign Base Addresses.
  • Added new NoC Connection and Addressing Examples section.
  • Revised Simulating NoC Designs topic to describe initiator-to-target-connections by registration function calls.
2023.07.05 23.2
  • Updated throughout to reflect support for Platform Designer connection flow and NoC Assignment Editor connection flow.
  • Updated throughout to reflect HPS-EMIF IP support.
  • Added new NoC Switch and Link Detail topic.
  • Updated NoC Design Flow Options topic for latest flows and comparison table.
  • Added new NoC Initiators for Hard Processor Systems topic.
  • Added new NoC Targets for Hard Processor Systems topic.
  • Added new NoC Initiators for Fabric AXI4 Managers topic.
  • Added new NoC Targets for Fabric AXI4 Managers topic.
  • Added new Connecting NoC IP and Assigning Base Addresses in the Platform Designer Connection Flow topic.
  • Added new Connecting NoC IP and Assigning Base Addresses in the NoC Assignment Editor Connection Flow topic.
  • Revised Connectivity Guidelines: NoC Initiators for Fabric AXI4 Managers topic.
  • Revised Connectivity Guidelines: NoC Targets for Fabric AXI4 Managers topic.
  • Added new Connectivity Guidelines: NoC Initiators for HPS topic.
  • Added new Connectivity Guidelines: NoC Targets for HPS
2023.05.22 23.1

Initial document release.
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