Intel Agilex® 7 LVDS SERDES User Guide: M-Series

ID 768615
Date 11/28/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

6.2. LVDS SERDES Source-Synchronous Timing Budget

The basis of the source synchronous timing analysis is the skew between the data and the clock signals instead of the clock-to-output setup times. High-speed differential data transmission requires the use of timing parameters provided by IC vendors and is strongly influenced by board skew, cable skew, and clock jitter.