2. Best Practices for Floorplanning Partial Reconfiguration Designs
This application note describes a practical approach and best practices for floorplanning the dynamic reconfiguration areas and structuring the RTL coding for optimization of partial reconfiguration designs in the Intel® Quartus® Prime Pro Edition software.
PR allows you to reconfigure a portion of an Intel® FPGA dynamically, while the remaining FPGA continues to operate. PR can implement multiple personas in a particular region in your design, without impacting operation in other areas.
Figure 1. Partial Reconfiguration Design
PR has wide use in datacenter applications that partition most of the core logic into one or more PR partitions, and then configure the periphery logic (that is, hard periphery IPs) in the static region(s). However, if not carefully planned, such designs can contain thousands of PR boundary ports crossing PR region boundaries. Also, sometimes designers divide the static regions into isolated parts of the chip, near fixed locations of the hard periphery elements. These conditions can reduce timing performance.
You can apply the techniques in this application note to help improve performance and reduce the chance of compilation errors during PR implementation.