AN 992: Best Practices for Floorplanning Partial Reconfiguration Designs

Download PDF
ID 764994
Date 2/21/2023
Public
Document Table of Contents
Document Table of Contents x
1. Answers to Top FAQs 2. Best Practices for Floorplanning Partial Reconfiguration Designs
2. Best Practices for Floorplanning Partial Reconfiguration Designs x
2.1. Document Prerequisites 2.2. Best Practice PR Design Techniques 2.3. Document Revision History of AN 992: Best Practices for Floorplanning Partial Reconfiguration Designs
2.2. Best Practice PR Design Techniques x
2.2.1. Technique 1: Use Joint Periphery Placement Regions 2.2.2. Technique 2: Lock Down the Periphery Elements 2.2.3. Technique 3: Reduce Data Connections Across Logic Lock Boundaries 2.2.4. Technique 4: Lock Down PR Boundary Ports
1. Answers to Top FAQs
2. Best Practices for Floorplanning Partial Reconfiguration Designs

2.2.3. Technique 3: Reduce Data Connections Across Logic Lock Boundaries

If the static region is thin and the floorplan has disjointed regions, you must carefully plan which IP should be in each region, and how to transfer data between disjointed periphery areas. Pipeline and duplicate these signals, according to the location of their destination nodes to reduce the signals crossing the PR region. Consider these signals:

  1. Control signals—fanning out to each periphery element, such as reset and enable. Duplicate and pipeline these signals to each isolated region to reduce signals crossing the PR region.
  2. Management bus—fanning out to each periphery element and multiple instances inside the PR region. This wide data bus affects performance because the fan-out spreads chip-wide to every design module.
  3. Data buses between static regions—data buses traveling from one static region to another isolated static region, separated by a PR region, require long routing resources that affect the design performance and cause routing congestion.
Floorplan 6 in High Fan-Out Bus Organization Reduces Connections Across Isolated Areas shows an example floorplan before optimization. The source module (mgmt bus) fan-outs to both of the modules in the static region (PCIe mgmt and EMIF mgmt) and to the PR region. While the example shows only two mgmt modules, a design can have more than two. Unless you plan carefully, many routings may cross the PR region and affect the performance of implementation versions.
Figure 4. High Fan-Out Bus Organization Reduces Connections Across Isolated Areas


Floorplan 7 in High Fan-Out Bus Organization Reduces Connections Across Isolated Areas shows how implementation of the following techniques in the static and PR region prevents many routings crossing the PR region that affect the performance of implementation versions:

  • Static region—insert a pipeline register to address the problem of the far distance from the mgmt bus to EMIF mgmt.
  • PR region— first bring in the signals to the PR region through pipelining, and then distribute the signals to the respective destination nodes. This method is much more effective than having multiple fan-outs directly from the mgmt bus in the static region to the destination in PR region.
  • Data buses between static regions—add pipeline registers in the PR region to ease placement and routing for the target performance, as Example of Data Connection Across PR Region shows.
  • Figure 5. Example of Data Connection Across PR Region


Related Information
Level Two Title