AN 992: Best Practices for Floorplanning Partial Reconfiguration Designs

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ID 764994
Date 2/21/2023
Public
Document Table of Contents
Document Table of Contents x
1. Answers to Top FAQs 2. Best Practices for Floorplanning Partial Reconfiguration Designs
2. Best Practices for Floorplanning Partial Reconfiguration Designs x
2.1. Document Prerequisites 2.2. Best Practice PR Design Techniques 2.3. Document Revision History of AN 992: Best Practices for Floorplanning Partial Reconfiguration Designs
2.2. Best Practice PR Design Techniques x
2.2.1. Technique 1: Use Joint Periphery Placement Regions 2.2.2. Technique 2: Lock Down the Periphery Elements 2.2.3. Technique 3: Reduce Data Connections Across Logic Lock Boundaries 2.2.4. Technique 4: Lock Down PR Boundary Ports
1. Answers to Top FAQs
2. Best Practices for Floorplanning Partial Reconfiguration Designs

2.2.4. Technique 4: Lock Down PR Boundary Ports

If you do not lock down the PR boundary ports (IOPORTs), the Intel® Quartus® Prime Fitter tends to distribute these ports based on the source and destination placement, as Floorplan 8 and Floorplan 9 show in Distribution of Ports with Locked and Unlocked I/O Ports. While this distribution might be the best placement for the current compiled persona, it might not be suitable for another persona, and could even negatively affect the performance.

Note: For more details on how to lock down I/O ports, refer to Creating Wrapper Logic for PR Regions in Intel® Quartus® Prime Pro Edition User Guide: Partial Reconfiguration.

Therefore, it is best to lock down the PR boundary ports to increase consistent performance across different PR personas, although this might not be the best placement for a dedicated persona. When using this method, the PR region appears as the entire chip with thousands of I/O ports along the boundary, which is more suitable for multiple different personas, as Floorplan 10 shows.

Figure 6. Distribution of Ports with Locked and Unlocked I/O Ports


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