In a PR-based design, you assign the hard peripheral interface to the non-changing static partition, and you configure the FPGA fabric core logic as the reconfigurable logic for partial reconfiguration.

This application note provides guidelines and techniques about the following to help optimize performance for PR designs:

• How to plan Logic Lock placement constraints to preserve the performance of the periphery elements.
• How to organize the signals fanning out to isolated regions that go through the PR region.
• How to organize the data connection between the isolated regions that pass through the PR regions, which has a timing effect on the implementation revision.
• How to adapt the static region to different personas and preserve the performance consistently.
• How to plan for a PR region and perform coding optimization accordingly.

One challenging application for PR design is with datacenter applications. In such applications, designers often configure the PR region to be as large as possible. This configuration causes the area of the static region to be compacted, with very high logic resource utilization. In addition, the locations of the hard peripheral interfaces are fixed and distributed across the chip, while occupying a small amount of associated core logic resources. These factors can have a negative impact on design performance. This document uses the data center application to illustrate PR best practices. You can also apply these techniques to other applications.

For example, the Intel® Agilex™ device family has the PCIe interface on the left side of the chip. The high-speed Ethernet interface is on the right side of the chip. The EMIF interface is on the upper and lower sides of the chip. Due to these physical location constraints, there is a natural tendency to constrain PR region placement using irregular Logic Lock region shapes. This problem becomes worse if your design divides the static region into multiple parts.