If you do not explicitly define Logic Lock region constraints for the peripheral IP, the Intel® Quartus® Prime Fitter places these elements across the regions by default, as Floorplan 4 shows in Figure 3. Floorplan 4 shows unconstrained, inefficient placement of the HSSI in the PCIe region of the chip, and placement of the EMIF in the HSSI area of the chip.

You can significantly improve performance in such example by manually locking down the peripheral logic using Logic Lock regions, according to the corresponding hard element locations. This technique is especially beneficial when the static region is thin and has disjointed areas, such as in Floorplan 4.

Floorplan 5 shows how locking down the PCIe periphery related entities to the static region, locking down the Ethernet periphery related entities to the static region on the right side of Floorplan 5, and locking down the EMIF periphery elements to the top and bottom static regions in Floorplan 5 improves routing efficiency. Performance improvement occurs because the static region is not over utilized, and the Fitter can more simply place the periphery IPs into the dedicated target areas, as Floorplan 5 shows.

Locking down these periphery elements resolves the timing performance bottlenecks caused by long paths across the regions.