AN 992: Best Practices for Floorplanning Partial Reconfiguration Designs

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ID 764994
Date 2/21/2023
Public
Document Table of Contents
Document Table of Contents x
1. Answers to Top FAQs 2. Best Practices for Floorplanning Partial Reconfiguration Designs
2. Best Practices for Floorplanning Partial Reconfiguration Designs x
2.1. Document Prerequisites 2.2. Best Practice PR Design Techniques 2.3. Document Revision History of AN 992: Best Practices for Floorplanning Partial Reconfiguration Designs
2.2. Best Practice PR Design Techniques x
2.2.1. Technique 1: Use Joint Periphery Placement Regions 2.2.2. Technique 2: Lock Down the Periphery Elements 2.2.3. Technique 3: Reduce Data Connections Across Logic Lock Boundaries 2.2.4. Technique 4: Lock Down PR Boundary Ports
1. Answers to Top FAQs
2. Best Practices for Floorplanning Partial Reconfiguration Designs

1. Answers to Top FAQs

Updated for:
Intel® Quartus® Prime Design Suite 22.4

What is partial reconfiguration (PR)?

Introduction

What prerequisites are there?

Document Prerequisites

What limits PR design performance?

Best Practice PR Design Techniques

How do I floorplan for PR?

Use Joint Periphery Placement Regions

How do I constrain the periphery?

Lock Down Periphery Elements

How do I improve PR persona performance?

Lock Down PR Boundary Ports

What are the known issues?

Intel FPGA Support Forums: PR

Do you have training on PR?

Intel FPGA Technical Training Catalog

Level Two Title