Agilex™ 5 FPGAs and SoCs Device Overview

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ID 762191
Date 9/06/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview of the Agilex™ 5 FPGAs and SoCs 2. Agilex™ 5 FPGAs and SoCs Family Plan 3. Second Generation Hyperflex® Core Architecture 4. Adaptive Logic Module in Agilex™ 5 FPGAs and SoCs 5. Internal Embedded Memory in Agilex™ 5 FPGAs and SoCs 6. Variable-Precision DSP in Agilex™ 5 FPGAs and SoCs 7. Core Clock Network in Agilex™ 5 FPGAs and SoCs 8. General Purpose I/Os in Agilex™ 5 FPGAs and SoCs 9. I/O PLLs in Agilex™ 5 FPGAs and SoCs 10. External Memory Interface in Agilex™ 5 FPGAs and SoCs 11. Hard Processor System in Agilex™ 5 SoCs 12. Transceivers in Agilex™ 5 FPGAs and SoCs 13. MIPI* Protocols Support in Agilex™ 5 FPGAs and SoCs 14. Variable Pitch BGA (VPBGA) Package Design of Agilex™ 5 FPGAs and SoCs 15. Configuration via Protocol Using PCIe* for Agilex™ 5 FPGAs and SoCs 16. Device Configuration and the SDM in Agilex™ 5 FPGAs and SoCs 17. Partial and Dynamic Configuration of Agilex™ 5 FPGAs and SoCs 18. Device Security for Agilex™ 5 FPGAs and SoCs 19. SEU Error Detection and Correction in Agilex™ 5 FPGAs and SoCs 20. Power Management for Agilex™ 5 FPGAs and SoCs 21. Software and Tools for Agilex™ 5 FPGAs and SoCs 22. Revision History for the Agilex™ 5 FPGAs and SoCs Device Overview
1. Overview of the Agilex™ 5 FPGAs and SoCs x
1.1. Key Features and Innovations in Agilex™ 5 FPGAs and SoCs 1.2. Agilex™ 5 FPGAs and SoCs Block Diagram 1.3. Agilex™ 5 FPGAs and SoCs Summary of Features 1.4. Additional Features for Agilex™ 5 SoCs
2. Agilex™ 5 FPGAs and SoCs Family Plan x
2.1. Agilex™ 5 FPGAs and SoCs D-Series 2.2. Agilex™ 5 FPGAs and SoCs E-Series 2.3. Agilex™ 5 FPGAs and SoCs Package Options 2.4. Part Number Decoder
10. External Memory Interface in Agilex™ 5 FPGAs and SoCs x
10.1. External Memory Interface Performance 10.2. Features of the Hard Memory Controller
12. Transceivers in Agilex™ 5 FPGAs and SoCs x
12.1. PMA Features in Agilex™ 5 FPGA GTS Transceivers 12.2. PCS Features in Agilex™ 5 FPGA GTS Transceivers 12.3. GTS Transceiver PLL in Agilex™ 5 FPGAs and SoCs
1. Overview of the Agilex™ 5 FPGAs and SoCs
2. Agilex™ 5 FPGAs and SoCs Family Plan
3. Second Generation Hyperflex® Core Architecture
4. Adaptive Logic Module in Agilex™ 5 FPGAs and SoCs
5. Internal Embedded Memory in Agilex™ 5 FPGAs and SoCs
6. Variable-Precision DSP in Agilex™ 5 FPGAs and SoCs
7. Core Clock Network in Agilex™ 5 FPGAs and SoCs
8. General Purpose I/Os in Agilex™ 5 FPGAs and SoCs
9. I/O PLLs in Agilex™ 5 FPGAs and SoCs
10. External Memory Interface in Agilex™ 5 FPGAs and SoCs
11. Hard Processor System in Agilex™ 5 SoCs
12. Transceivers in Agilex™ 5 FPGAs and SoCs
13. MIPI* Protocols Support in Agilex™ 5 FPGAs and SoCs
14. Variable Pitch BGA (VPBGA) Package Design of Agilex™ 5 FPGAs and SoCs
15. Configuration via Protocol Using PCIe* for Agilex™ 5 FPGAs and SoCs
16. Device Configuration and the SDM in Agilex™ 5 FPGAs and SoCs
17. Partial and Dynamic Configuration of Agilex™ 5 FPGAs and SoCs
18. Device Security for Agilex™ 5 FPGAs and SoCs
19. SEU Error Detection and Correction in Agilex™ 5 FPGAs and SoCs
20. Power Management for Agilex™ 5 FPGAs and SoCs
21. Software and Tools for Agilex™ 5 FPGAs and SoCs
22. Revision History for the Agilex™ 5 FPGAs and SoCs Device Overview

12. Transceivers in Agilex™ 5 FPGAs and SoCs

The Agilex™ 5 FPGAs and SoCs are equipped with NRZ transceivers optimized for a wide variety of applications, ranging from 1 Gbps to 28.1 Gbps NRZ.

The monolithic GTS transceivers in Agilex™ 5 FPGAs and SoCs enable low latencies for edge or mid-range FPGA applications. For long reach backplane-driving applications, the devices use advanced adaptive equalization circuits to equalize system loss.

All Agilex™ 5 FPGA GTS transceiver channels are equipped with these blocks:

  • Dedicated PMA—provides primary interfacing capabilities to physical channels.
  • Hardened PCS—supports 64b/66b encoding and decoding functions, data scrambling, block alignment, and gearboxing functions.
  • FEC—Firecode FEC for 10/25 GbE BASE-KR/CR applications and Reed Solomon FEC.

A single PMA–PCS channel with independent clock domains forms each GTS transceiver channel. Using a highly configurable clock distribution network, you can configure various bonded and non-bonded data rate within each GTS transceiver bank.

Figure 10. D-Series FPGAs GTS Transceiver Block Diagrams


Figure 11. E-Series FPGAs GTS Transceiver Block Diagrams


Table 20.  Capabilities of FPGA GTS Transceivers in Agilex™ 5 FPGAs and SoCs
Capability Maximum Specification
D-Series FPGA E-Series FPGA
Device Group A Device Group B
Maximum speed

28.1 Gbps NRZ

(1–28.1 Gbps continuous)

28.1 Gbps NRZ

(1–28.1 Gbps continuous)

17.16 Gbps NRZ

(1–17.16 Gbps continuous)
FEC

10/25 GbE FEC direct mode

(IEEE 802.3 Clause 74 Firecode FEC and Clause 91 RS-FEC hard IPs)

10/25 GbE FEC direct mode

(IEEE 802.3 Clause 74 Firecode FEC and Clause 91 RS-FEC hard IPs)

10 GbE FEC direct mode

(IEEE 802.3 Clause 74 Firecode FEC hard IP)

PCS

10/25 GbE PCS direct mode19

(64b/66b hard IP)

10/25 GbE PCS direct mode19

(64b/66b hard IP)

10 GbE PCS direct mode19

(64b/66b hard IP)
PCIe*
  • PCIe* 4.0 ×8 controller hard IP
  • PCIe* 4.0 ×4 controller hard IP
PCIe* 4.0 ×4 controller hard IP Up to PCIe* 4.0 ×4 controller hard IP

Transmitter/

Receiver

 Independent transmitter and receiver to support combining simplex protocols
PMA

PMA direct mode (bypass Ethernet and PCIe* hard IPs)


Section Content
PMA Features in Agilex 5 FPGA GTS Transceivers
PCS Features in Agilex 5 FPGA GTS Transceivers
GTS Transceiver PLL in Agilex 5 FPGAs and SoCs

19 The PCS direct mode is supported on GbE and other protocols.
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