Agilex™ 5 FPGAs and SoCs Device Overview

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ID 762191
Date 9/06/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview of the Agilex™ 5 FPGAs and SoCs 2. Agilex™ 5 FPGAs and SoCs Family Plan 3. Second Generation Hyperflex® Core Architecture 4. Adaptive Logic Module in Agilex™ 5 FPGAs and SoCs 5. Internal Embedded Memory in Agilex™ 5 FPGAs and SoCs 6. Variable-Precision DSP in Agilex™ 5 FPGAs and SoCs 7. Core Clock Network in Agilex™ 5 FPGAs and SoCs 8. General Purpose I/Os in Agilex™ 5 FPGAs and SoCs 9. I/O PLLs in Agilex™ 5 FPGAs and SoCs 10. External Memory Interface in Agilex™ 5 FPGAs and SoCs 11. Hard Processor System in Agilex™ 5 SoCs 12. Transceivers in Agilex™ 5 FPGAs and SoCs 13. MIPI* Protocols Support in Agilex™ 5 FPGAs and SoCs 14. Variable Pitch BGA (VPBGA) Package Design of Agilex™ 5 FPGAs and SoCs 15. Configuration via Protocol Using PCIe* for Agilex™ 5 FPGAs and SoCs 16. Device Configuration and the SDM in Agilex™ 5 FPGAs and SoCs 17. Partial and Dynamic Configuration of Agilex™ 5 FPGAs and SoCs 18. Device Security for Agilex™ 5 FPGAs and SoCs 19. SEU Error Detection and Correction in Agilex™ 5 FPGAs and SoCs 20. Power Management for Agilex™ 5 FPGAs and SoCs 21. Software and Tools for Agilex™ 5 FPGAs and SoCs 22. Revision History for the Agilex™ 5 FPGAs and SoCs Device Overview
1. Overview of the Agilex™ 5 FPGAs and SoCs x
1.1. Key Features and Innovations in Agilex™ 5 FPGAs and SoCs 1.2. Agilex™ 5 FPGAs and SoCs Block Diagram 1.3. Agilex™ 5 FPGAs and SoCs Summary of Features 1.4. Additional Features for Agilex™ 5 SoCs
2. Agilex™ 5 FPGAs and SoCs Family Plan x
2.1. Agilex™ 5 FPGAs and SoCs D-Series 2.2. Agilex™ 5 FPGAs and SoCs E-Series 2.3. Agilex™ 5 FPGAs and SoCs Package Options 2.4. Part Number Decoder
10. External Memory Interface in Agilex™ 5 FPGAs and SoCs x
10.1. External Memory Interface Performance 10.2. Features of the Hard Memory Controller
12. Transceivers in Agilex™ 5 FPGAs and SoCs x
12.1. PMA Features in Agilex™ 5 FPGA GTS Transceivers 12.2. PCS Features in Agilex™ 5 FPGA GTS Transceivers 12.3. GTS Transceiver PLL in Agilex™ 5 FPGAs and SoCs
1. Overview of the Agilex™ 5 FPGAs and SoCs
2. Agilex™ 5 FPGAs and SoCs Family Plan
3. Second Generation Hyperflex® Core Architecture
4. Adaptive Logic Module in Agilex™ 5 FPGAs and SoCs
5. Internal Embedded Memory in Agilex™ 5 FPGAs and SoCs
6. Variable-Precision DSP in Agilex™ 5 FPGAs and SoCs
7. Core Clock Network in Agilex™ 5 FPGAs and SoCs
8. General Purpose I/Os in Agilex™ 5 FPGAs and SoCs
9. I/O PLLs in Agilex™ 5 FPGAs and SoCs
10. External Memory Interface in Agilex™ 5 FPGAs and SoCs
11. Hard Processor System in Agilex™ 5 SoCs
12. Transceivers in Agilex™ 5 FPGAs and SoCs
13. MIPI* Protocols Support in Agilex™ 5 FPGAs and SoCs
14. Variable Pitch BGA (VPBGA) Package Design of Agilex™ 5 FPGAs and SoCs
15. Configuration via Protocol Using PCIe* for Agilex™ 5 FPGAs and SoCs
16. Device Configuration and the SDM in Agilex™ 5 FPGAs and SoCs
17. Partial and Dynamic Configuration of Agilex™ 5 FPGAs and SoCs
18. Device Security for Agilex™ 5 FPGAs and SoCs
19. SEU Error Detection and Correction in Agilex™ 5 FPGAs and SoCs
20. Power Management for Agilex™ 5 FPGAs and SoCs
21. Software and Tools for Agilex™ 5 FPGAs and SoCs
22. Revision History for the Agilex™ 5 FPGAs and SoCs Device Overview

13. MIPI* Protocols Support in Agilex™ 5 FPGAs and SoCs

The Agilex™ 5 FPGAs and SoCs support native MIPI* IP D-PHY* . The devices support MIPI* D-PHY* v2.5 at up to 3.5 Gbps20 per lane. The Agilex™ 5 FPGAs support MIPI* D-PHY* high-speed and low-power signaling modes without requiring external components.

Features of the MIPI* IP D-PHY* :

  • Enables unidirectional multi-lane configurations—1, 2, 4, or 8 lanes
  • Supports low-power and high-speed signaling up to 3.5 Gbps 20 per lane

The MIPI* IP D-PHY* implements MIPI* transmit and receive interfaces for Agilex™ 5 FPGAs in accordance to the following protocols:

  • Camera Serial Interface (CSI-2) version 3.0 with underlying D-PHY* standard
  • Display Serial Interface (DSI-2) version 2.0 with underlying D-PHY* standard
Table 23.   MIPI* CSI-2 and DSI-2 Performance in Agilex™ 5 FPGAs and SoCs
Protocol D-Series FPGA E-Series FPGA
Device Group A Device Group B
CSI-2
  • CSI-2 version 3, up to eight lanes
  • D-PHY* v2.5 at up to 3.5 Gbps 20
  • CSI-2 version 3, up to eight lanes
  • D-PHY* v2.5 at up to 3.5 Gbps 20
  • CSI-2 version 3, up to eight lanes
  • D-PHY* v2.5 at up to 2.5 Gbps21
DSI-2
  • DSI-2 version 2, up to four lanes
  • D-PHY* v2.5 at up to 3.5 Gbps
  • DSI-2 version 2, up to four lanes
  • D-PHY* v2.5 at up to 3.5 Gbps 20
  • DSI-2 version 2, up to four lanes
  • D-PHY* v2.5 at up to 2.5 Gbps21
Figure 12.  MIPI* Receiver Block Diagram


Figure 13.  MIPI* Transmitter Block Diagram


20 Up to 3.5 Gbps for standard reference channel, and up to 2.5 Gbps for long reference channel.
21 Up to 2.5 Gbps for standard reference and long reference channels.
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