Agilex™ 5 FPGAs and SoCs Device Overview

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ID 762191
Date 9/06/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview of the Agilex™ 5 FPGAs and SoCs 2. Agilex™ 5 FPGAs and SoCs Family Plan 3. Second Generation Hyperflex® Core Architecture 4. Adaptive Logic Module in Agilex™ 5 FPGAs and SoCs 5. Internal Embedded Memory in Agilex™ 5 FPGAs and SoCs 6. Variable-Precision DSP in Agilex™ 5 FPGAs and SoCs 7. Core Clock Network in Agilex™ 5 FPGAs and SoCs 8. General Purpose I/Os in Agilex™ 5 FPGAs and SoCs 9. I/O PLLs in Agilex™ 5 FPGAs and SoCs 10. External Memory Interface in Agilex™ 5 FPGAs and SoCs 11. Hard Processor System in Agilex™ 5 SoCs 12. Transceivers in Agilex™ 5 FPGAs and SoCs 13. MIPI* Protocols Support in Agilex™ 5 FPGAs and SoCs 14. Variable Pitch BGA (VPBGA) Package Design of Agilex™ 5 FPGAs and SoCs 15. Configuration via Protocol Using PCIe* for Agilex™ 5 FPGAs and SoCs 16. Device Configuration and the SDM in Agilex™ 5 FPGAs and SoCs 17. Partial and Dynamic Configuration of Agilex™ 5 FPGAs and SoCs 18. Device Security for Agilex™ 5 FPGAs and SoCs 19. SEU Error Detection and Correction in Agilex™ 5 FPGAs and SoCs 20. Power Management for Agilex™ 5 FPGAs and SoCs 21. Software and Tools for Agilex™ 5 FPGAs and SoCs 22. Revision History for the Agilex™ 5 FPGAs and SoCs Device Overview
1. Overview of the Agilex™ 5 FPGAs and SoCs x
1.1. Key Features and Innovations in Agilex™ 5 FPGAs and SoCs 1.2. Agilex™ 5 FPGAs and SoCs Block Diagram 1.3. Agilex™ 5 FPGAs and SoCs Summary of Features 1.4. Additional Features for Agilex™ 5 SoCs
2. Agilex™ 5 FPGAs and SoCs Family Plan x
2.1. Agilex™ 5 FPGAs and SoCs D-Series 2.2. Agilex™ 5 FPGAs and SoCs E-Series 2.3. Agilex™ 5 FPGAs and SoCs Package Options 2.4. Part Number Decoder
10. External Memory Interface in Agilex™ 5 FPGAs and SoCs x
10.1. External Memory Interface Performance 10.2. Features of the Hard Memory Controller
12. Transceivers in Agilex™ 5 FPGAs and SoCs x
12.1. PMA Features in Agilex™ 5 FPGA GTS Transceivers 12.2. PCS Features in Agilex™ 5 FPGA GTS Transceivers 12.3. GTS Transceiver PLL in Agilex™ 5 FPGAs and SoCs
1. Overview of the Agilex™ 5 FPGAs and SoCs
2. Agilex™ 5 FPGAs and SoCs Family Plan
3. Second Generation Hyperflex® Core Architecture
4. Adaptive Logic Module in Agilex™ 5 FPGAs and SoCs
5. Internal Embedded Memory in Agilex™ 5 FPGAs and SoCs
6. Variable-Precision DSP in Agilex™ 5 FPGAs and SoCs
7. Core Clock Network in Agilex™ 5 FPGAs and SoCs
8. General Purpose I/Os in Agilex™ 5 FPGAs and SoCs
9. I/O PLLs in Agilex™ 5 FPGAs and SoCs
10. External Memory Interface in Agilex™ 5 FPGAs and SoCs
11. Hard Processor System in Agilex™ 5 SoCs
12. Transceivers in Agilex™ 5 FPGAs and SoCs
13. MIPI* Protocols Support in Agilex™ 5 FPGAs and SoCs
14. Variable Pitch BGA (VPBGA) Package Design of Agilex™ 5 FPGAs and SoCs
15. Configuration via Protocol Using PCIe* for Agilex™ 5 FPGAs and SoCs
16. Device Configuration and the SDM in Agilex™ 5 FPGAs and SoCs
17. Partial and Dynamic Configuration of Agilex™ 5 FPGAs and SoCs
18. Device Security for Agilex™ 5 FPGAs and SoCs
19. SEU Error Detection and Correction in Agilex™ 5 FPGAs and SoCs
20. Power Management for Agilex™ 5 FPGAs and SoCs
21. Software and Tools for Agilex™ 5 FPGAs and SoCs
22. Revision History for the Agilex™ 5 FPGAs and SoCs Device Overview

22. Revision History for the Agilex™ 5 FPGAs and SoCs Device Overview

Document Version Changes
2024.09.06
  • Added support for ACE5-Lite cache stashing for the FPGA–to–HPS bridge.
  • Updated the variable precision DSP support with up to 4.69 TFLOPS.
  • Updated the B15A VPBGA package pin counts from 324 to 351.
2024.08.16
  • Replaced package B23A to B23D in the D-Series package options.
  • Replaced package B32A to B32B in the D-Series package options.
  • Updated the Variable Pitch BGA (VPBGA) information to clarify that the VPBGA ball pitch is variable, ranging from 0.65 mm to 1.45 mm in a single package to ease signal routing.
  • Updated Figure: Comparison Between Standard BGA and VPBGA and Figure: Example of PCB Trace Routing for Variable Pitch BGA (VPBGA) Package.
2024.04.01
  • Added the adaptive logic module (ALM) counts.
  • Removed package M16A from the A5E 028B device.
  • Retitled the "Available Options" topic to "Part Number Decoder".
2024.01.12
  • Added 1.0 V LVCMOS support for the HSIO.
  • Added notes that the minimum ball pitch of 0.65 mm is not meant for signal trace routing.
  • Updated the fabric-feeding I/O PLL count for the following devices:
    • A5D 051 and A5D 064—from 13 to 15
    • A5E 043A and A5E 043B—from 11 to 13
  • Added a figure that shows the available ordering part numbers.
  • Removed support for ACE5-Lite cache stashing for the FPGA–to–HPS bridge.
2023.09.18
  • Updated references to "Balls Anywhere" to "Variable Pitch BGA (VPBGA)".
  • Updated the package options and vertical migrations for E-Series FPGAs to remove information about conditional migration path.
2023.05.15
  • Updated the package options and vertical migrations:
    • Added package B18A.
    • Updated pin counts for packages B23B, B23A, and B32A.
    • Added devices to package B23A of the E-Series FPGA Device Group A.
  • Updated the supported DDR4 maximum width for E-Series FPGAs.
  • Updated E-Series FPGA Device Group B to support up to PCIe 4.0.
  • Assigned "GTS" naming to the transceivers.
  • Updated information about the HPS L2 cache.
  • Updated the E-Series HPS processors speeds:
    • Dual core ARM® Cortex®-A76—from up to 1.6 GHz to up to:
      • Device Group A—1.8 GHz
      • Device Group B— 1.4 GHz
    • Dual core ARM® Cortex®-A55—from up to 1.33 GHz to up to:
      • Device Group A—1.5 GHz
      • Device Group B— 1.25 GHz
  • Updated the HPS block diagram.
  • Removed ONFI 3.x and 4.x from HPS NAND flash controller.
  • Updated HPS Ethernet MAC information:
    • Updated the TSN endpoint functionality compliance.
    • Removed MII, RMII, and GMII support.
    • Updated RGMII support.
2023.01.10 Initial release.
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