Visible to Intel only — GUID: bii1666133092409
Ixiasoft
Partial Reconfiguration External Configuration Controller Intel FPGA IP
Reference Design Requirements
Reference Design Walkthrough
Hardware Testing Flow
Document Revision History for AN 991: Partial Reconfiguration via Configuration Pins (External Host) Reference Design for Intel® Agilex® F-Series FPGA Development Board
Step 1: Getting Started
Step 2: Creating a Design Partition
Step 3: Allocating Placement and Routing Region for a PR Partition
Step 4: Adding the Partial Reconfiguration External Configuration Controller Intel FPGA IP
Step 5: Defining Personas
Step 6: Creating Revisions
Step 7: Compiling the Base Revision
Step 8: Preparing PR Implementation Revisions
Step 9: Programming the Board
Visible to Intel only — GUID: bii1666133092409
Ixiasoft
Reference Design Walkthrough
The following steps describe implementation of partial reconfiguration via configuration pins (external host) on the Intel® Agilex® F-Series FPGA development board:
- Step 1: Getting Started
- Step 2: Creating a Design Partition
- Step 3: Allocating Placement and Routing Regions
- Step 4: Adding the Partial Reconfiguration External Configuration Controller IP
- Step 5: Defining Personas
- Step 6: Creating Revisions
- Step 7: Compiling the Base Revision
- Step 8: Preparing PR Implementation Revisions
- Step 9: Programming the Board
Section Content
Step 1: Getting Started
Step 2: Creating a Design Partition
Step 3: Allocating Placement and Routing Region for a PR Partition
Step 4: Adding the Partial Reconfiguration External Configuration Controller Intel FPGA IP
Step 5: Defining Personas
Step 6: Creating Revisions
Step 7: Compiling the Base Revision
Step 8: Preparing PR Implementation Revisions
Step 9: Programming the Board