AN 991: Partial Reconfiguration via Configuration Pins (External Host) Reference Design: for Intel® Agilex® F-Series FPGA Development Board

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ID 750856
Date 11/14/2022
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Document Table of Contents
Document Table of Contents x
1. Answers to Top FAQs AN 991: Partial Reconfiguration via Configuration Pins (External Host) Reference Design
AN 991: Partial Reconfiguration via Configuration Pins (External Host) Reference Design x
Partial Reconfiguration External Configuration Controller Intel FPGA IP Reference Design Requirements Reference Design Walkthrough Hardware Testing Flow Document Revision History for AN 991: Partial Reconfiguration via Configuration Pins (External Host) Reference Design for Intel® Agilex® F-Series FPGA Development Board
Reference Design Walkthrough x
Step 1: Getting Started Step 2: Creating a Design Partition Step 3: Allocating Placement and Routing Region for a PR Partition Step 4: Adding the Partial Reconfiguration External Configuration Controller Intel FPGA IP Step 5: Defining Personas Step 6: Creating Revisions Step 7: Compiling the Base Revision Step 8: Preparing PR Implementation Revisions Step 9: Programming the Board
Step 4: Adding the Partial Reconfiguration External Configuration Controller Intel FPGA IP x
Updating the Top-Level Design
Step 6: Creating Revisions x
Setting the Base Revision Type Creating Implementation Revisions
1. Answers to Top FAQs
AN 991: Partial Reconfiguration via Configuration Pins (External Host) Reference Design

Hardware Testing Flow

The following sequences describe the reference design hardware testing flow.

Figure 12. Intel Agilex Device External Host Hardware Setup


Step 1: Program the Helper FPGA (External Host)

The following sequence describes programming the helper FPGA that operates as the PR process external host:

  1. Specify the Avalon® streaming interface setting that corresponds with the mode that you select (x8, x16, or x32).
  2. Initialize the platform by programming the helper FPGA using the Intel® Quartus® Prime Programmer and connected configuration cable.
  3. Using the helper FPGA, read the CONF_DONE and AVST_READY signals. CONF_DONE should be 0, AVST_READY should be 1. Logic high on this pin indicates the SDM is ready to accept data from an external host. This output is part of the SDM I/O.
    Note: The CONF_DONE pin signals an external host that bitstream transfer is successful. Use these signals only to monitor the full chip configuration process. Refer to the Intel Agilex Configuration User Guide for more information on this pin.

Step 2: Program the DUT FPGA with Full Chip SOF via External Host

The following sequence describes programming the DUT FPGA with the full chip SRAM Object File (.sof) using the host Avalon® streaming interface:

  1. Write the full chip bitstream into the DDR4 external memory of the helper FPGA (external host).
  2. Configure the DUT FPGA with the full chip .sof using the Avalon® streaming interface (x8, x16, x32).
  3. Read the status DUT FPGA configuration signals. CONF_DONE should be 1, AVST_READY should be 0.
Figure 13. Timing Specifications: Partial Reconfiguration External Controller Intel FPGA IP


Step 3: Program the DUT FPGA with the First Persona via External Host

  1. Apply the freeze on the target PR region in the DUT FPGA.
  2. Using the Intel® Quartus® Prime System Console, assert pr_request to start the partial reconfiguration. AVST_READY should be 1.
  3. Write the first PR persona bitstream into the DDR4 external memory of the helper FPGA (external host).
  4. Using Avalon® streaming interface (x8, x16, x32), reconfigure the DUT FPGA with the first persona bitstream.
  5. To monitor the PR status, click Tools > System Console to launch System Console. In System Console, monitor the PR status:
    • pr_error is 2—reconfiguration in process.
    • pr_error is 3—reconfiguration is complete.
  6. Apply unfreeze on the PR region in the DUT FPGA.
Note: If an error occurs during PR operation, such as failure in version checking or authorization checking, the PR operation terminates.
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