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Partial Reconfiguration External Configuration Controller Intel FPGA IP
Reference Design Requirements
Reference Design Walkthrough
Hardware Testing Flow
Document Revision History for AN 991: Partial Reconfiguration via Configuration Pins (External Host) Reference Design for Intel® Agilex® F-Series FPGA Development Board
Step 1: Getting Started
Step 2: Creating a Design Partition
Step 3: Allocating Placement and Routing Region for a PR Partition
Step 4: Adding the Partial Reconfiguration External Configuration Controller Intel FPGA IP
Step 5: Defining Personas
Step 6: Creating Revisions
Step 7: Compiling the Base Revision
Step 8: Preparing PR Implementation Revisions
Step 9: Programming the Board
Visible to Intel only — GUID: bsv1666136164584
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Creating Implementation Revisions
- To open the Revisions dialog box, click Project > Revisions.
- To create a new revision, double-click <<new revision>>.
- In Revision name, specify blinking_led_default and select blinking_led for Based on revision.
- For the Revision type, select Partial Reconfiguration - Persona Implementation.
Figure 7. Creating Revisions
- Similarly, set the Revision type for blinking_led_slow and blinking_led_empty revisions.
- Verify that each .qsf file now contains the following assignment:
where, place_holder is the default entity name for the newly created PR implementation revision.set_global_assignment -name REVISION_TYPE PR_IMPL set_instance_assignment -name ENTITY_REBINDING \ place_holder -to u_blinking_led
Figure 8. Project Revisions