AN 991: Partial Reconfiguration via Configuration Pins (External Host) Reference Design: for Intel Agilex® 7 FPGA Development Board

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Date 2/14/2024
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Answers to Top FAQs AN 991: Partial Reconfiguration via Configuration Pins (External Host) Reference Design for Intel Agilex® 7 FPGA Development Board
AN 991: Partial Reconfiguration via Configuration Pins (External Host) Reference Design for Intel Agilex® 7 FPGA Development Board x
Partial Reconfiguration External Configuration Controller Intel FPGA IP Reference Design Requirements Reference Design Walkthrough Hardware Testing Flow Document Revision History for AN 991: Partial Reconfiguration via Configuration Pins (External Host) Reference Design for Intel Agilex® 7 FPGA Development Board
Reference Design Walkthrough x
Step 1: Getting Started Step 2: Creating a Design Partition Step 3: Allocating Placement and Routing Region for a PR Partition Step 4: Adding the Partial Reconfiguration External Configuration Controller Intel FPGA IP Step 5: Defining Personas Step 6: Creating Revisions Step 7: Compiling the Base Revision Step 8: Preparing PR Implementation Revisions Step 9: Programming the Board
Step 4: Adding the Partial Reconfiguration External Configuration Controller Intel FPGA IP x
Updating the Top-Level Design
Step 6: Creating Revisions x
Setting the Base Revision Type Creating Implementation Revisions
Answers to Top FAQs
AN 991: Partial Reconfiguration via Configuration Pins (External Host) Reference Design for Intel Agilex® 7 FPGA Development Board

Step 9: Programming the Board

This tutorial uses an Intel Agilex® 7 F-Series or M-Series development board on the bench, outside of the PCIe* slot in your host machine. Before you program the board, ensure that you have completed the following steps:

  1. Connect the power supply to the Intel Agilex® 7 F-Series or M-Series development board.
  2. Connect the Intel® FPGA Download Cable between your PC USB port and the Intel® FPGA Download Cable port on the development board.

To run the design on the Intel Agilex® 7 F-Series or M-Series development board:

  1. Open the Intel® Quartus® Prime software and click Tools > Programmer.
  2. In the Programmer, click Hardware Setup and select USB-Blaster.
  3. Click Auto Detect and select the appropriate Intel Agilex® 7 device for your development board.
  4. Click OK. The Intel® Quartus® Prime software detects and updates the Programmer with the FPGA devices on the board.
  5. Select the appropriate Intel Agilex® 7 device for your development board, click Change File and load the blinking_led.sof.
  6. Enable Program/Configure for the blinking_led.sof file.
  7. Click Start and wait for the progress bar to reach 100%.
  8. To program only the PR region, right-click the blinking_led.sof file in the Programmer and click Add PR Programming File.
  9. Select the blinking_led_slow.pr_partition.rbf file.
  10. Disable Program/Configure for blinking_led.sof file.
  11. Enable Program/Configure for blinking_led_slow.pr_partition.rbf file and click Start. On the board, observe LED[0] and LED[1] continuing to blink. When the progress bar reaches 100%, LED[2] and LED[3] blink slower.
  12. To reprogram the PR region, right-click the .rbf file in the Programmer and click Change PR Programing File.
  13. Select the .rbf files for the other two personas to observe the behavior on the board. Loading the blinking_led_default.pr_partition.rbf file causes the LEDs to blink at a specific frequency, and loading the blinking_led_empty.pr_partition.rbf file causes the LEDs to stay ON.
Figure 11. Programming the Intel Agilex® 7 F-Series FPGA Development Board


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