AN 991: Partial Reconfiguration via Configuration Pins (External Host) Reference Design: for Intel Agilex® 7 FPGA Development Board

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Date 2/14/2024
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Answers to Top FAQs AN 991: Partial Reconfiguration via Configuration Pins (External Host) Reference Design for Intel Agilex® 7 FPGA Development Board
AN 991: Partial Reconfiguration via Configuration Pins (External Host) Reference Design for Intel Agilex® 7 FPGA Development Board x
Partial Reconfiguration External Configuration Controller Intel FPGA IP Reference Design Requirements Reference Design Walkthrough Hardware Testing Flow Document Revision History for AN 991: Partial Reconfiguration via Configuration Pins (External Host) Reference Design for Intel Agilex® 7 FPGA Development Board
Reference Design Walkthrough x
Step 1: Getting Started Step 2: Creating a Design Partition Step 3: Allocating Placement and Routing Region for a PR Partition Step 4: Adding the Partial Reconfiguration External Configuration Controller Intel FPGA IP Step 5: Defining Personas Step 6: Creating Revisions Step 7: Compiling the Base Revision Step 8: Preparing PR Implementation Revisions Step 9: Programming the Board
Step 4: Adding the Partial Reconfiguration External Configuration Controller Intel FPGA IP x
Updating the Top-Level Design
Step 6: Creating Revisions x
Setting the Base Revision Type Creating Implementation Revisions
Answers to Top FAQs
AN 991: Partial Reconfiguration via Configuration Pins (External Host) Reference Design for Intel Agilex® 7 FPGA Development Board

Step 2: Creating a Design Partition

You must create design partitions for each PR region that you want to partially reconfigure. The following steps create a design partition for the u_blinking_led instance.
Creating Design Partitions


  1. Right-click the u_blinking_led instance in the Project Navigator and click Design Partition > Reconfigurable. A design partition icon appears next to each instance that is set as a partition.
  2. Click Assignments > Design Partitions Window. The window displays all design partitions in the project.
  3. Edit the partition name in the Design Partitions Window by double-clicking the name. For this reference design, rename the partition name to pr_partition.
    Note: When you create a partition, the Intel® Quartus® Prime software automatically generates a partition name, based on the instance name and hierarchy path. This default partition name can vary with each instance.
  4. To export the finalized static region from the base revision compile, double-click the entry for root_partition in the Post Final Export File column, and type blinking_led_static.qdb.
    Figure 3. Exporting Post Final Snapshot

Verify that the blinking_led.qsf contains the following assignments, corresponding to your reconfigurable design partition: 

set_instance_assignment -name PARTITION pr_partition -to u_blinking_led
        set_instance_assignment -name PARTIAL_RECONFIGURATION_PARTITION ON \
        -to u_blinking_led

set_instance_assignment -name EXPORT_PARTITION_SNAPSHOT_FINAL \	
        blinking_led_static.qdb -to | -entity top
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