AN 991: Partial Reconfiguration via Configuration Pins (External Host) Reference Design: for Intel® Agilex® F-Series FPGA Development Board

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ID 750856
Date 11/14/2022
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Document Table of Contents
Document Table of Contents x
1. Answers to Top FAQs AN 991: Partial Reconfiguration via Configuration Pins (External Host) Reference Design
AN 991: Partial Reconfiguration via Configuration Pins (External Host) Reference Design x
Partial Reconfiguration External Configuration Controller Intel FPGA IP Reference Design Requirements Reference Design Walkthrough Hardware Testing Flow Document Revision History for AN 991: Partial Reconfiguration via Configuration Pins (External Host) Reference Design for Intel® Agilex® F-Series FPGA Development Board
Reference Design Walkthrough x
Step 1: Getting Started Step 2: Creating a Design Partition Step 3: Allocating Placement and Routing Region for a PR Partition Step 4: Adding the Partial Reconfiguration External Configuration Controller Intel FPGA IP Step 5: Defining Personas Step 6: Creating Revisions Step 7: Compiling the Base Revision Step 8: Preparing PR Implementation Revisions Step 9: Programming the Board
Step 4: Adding the Partial Reconfiguration External Configuration Controller Intel FPGA IP x
Updating the Top-Level Design
Step 6: Creating Revisions x
Setting the Base Revision Type Creating Implementation Revisions
1. Answers to Top FAQs
AN 991: Partial Reconfiguration via Configuration Pins (External Host) Reference Design

Step 5: Defining Personas

This reference design defines three separate personas for the single PR partition. To define and include the personas in your project:

  1. Create three SystemVerilog files, blinking_led.sv, blinking_led_slow.sv, and blinking_led_empty.sv in your working directory for the three personas.
    Table 3.  Reference Design Personas
    File Name Description Code
    blinking_led.sv Default persona with same design as the flat implementation 
    `timescale 1 ps / 1 ps
`default_nettype none


module blinking_led (
    // clock
    input wire clock,
    input wire [31:0] counter,

    // Control signals for the LEDs
    output wire led_two_on,
    output wire led_three_on
);

    localparam COUNTER_TAP = 23;

    reg led_two_on_r;
    reg led_three_on_r;
  
    assign led_two_on = led_two_on_r;
    assign led_three_on = led_three_on_r;

    always_ff @(posedge clock) 
    begin
        led_two_on_r <= counter[COUNTER_TAP];
        led_three_on_r <= counter[COUNTER_TAP];
    end

endmodule
    blinking_led_slow.sv LEDs blink slower 
    `timescale 1 ps / 1 ps
`default_nettype none

module blinking_led_slow (
    // clock
    input wire clock,
    input wire [31:0] counter,

    // Control signals for the LEDs
    output wire led_two_on,
    output wire led_three_on
);

    localparam COUNTER_TAP = 27;

    reg led_two_on_r;
    reg led_three_on_r;
 
    assign led_two_on = led_two_on_r;
    assign led_three_on = led_three_on_r;

    always_ff @(posedge clock) 
    begin
       led_two_on_r <= counter[COUNTER_TAP];
       led_three_on_r <= counter[COUNTER_TAP];
    end

endmodule
    blinking_led_empty.sv LEDs stay ON 
    `timescale 1 ps / 1 ps
`default_nettype none

module blinking_led_empty(
    // clock
    input wire clock,
    input wire [31:0] counter,

    // Control signals for the LEDs
    output wire led_two_on,
    output wire led_three_on
);

    // LED is active low 
    assign led_two_on = 1'b0;
    assign led_three_on = 1'b0;

endmodule
Note:
  • blinking_led.sv is already available as part of the files you copy from the flat/ sub-directory. You can simply reuse this file.
  • If you create the SystemVerilog files from the Intel® Quartus® Prime Text Editor, disable the Add file to current project option, when saving the files.
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