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1. About the RiscFree* IDE
2. Installation and Setup
3. Getting Started with RiscFree* IDE
4. Debug Setup for Nios® V Processor System
5. Debug Setup for Arm* Hard Processor System
6. Debugging with RiscFree* IDE
7. Ashling RiscFree* Integrated Development Environment (IDE) for Intel® FPGAs User Guide Archives
8. Document Revision History for the Ashling RiscFree* Integrated Development Environment (IDE) for Intel® FPGAs User Guide
A. Appendix
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6.3. Heterogeneous Multicore Debug
Heterogeneous multicore debugging is a method where you can debug two or more cores that differ in architecture or micro-architecture ( Nios® V core and Arm* HPS core) simultaneously in the same integrated development environment.
By using heterogeneous multicore debugging, you can do the following:
- Simultaneously debug the entire integrated system in a single IDE.
- Real-time control of multiple processor cores that interact with each other.
In this example, we use Nios® V "Hello World" project and HPS design example provided by Ashling.