Ashling* RiscFree* Integrated Development Environment (IDE) for Intel® FPGAs User Guide

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ID 730783
Date 10/31/2022
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Document Table of Contents
Document Table of Contents x
1. About the RiscFree* IDE 2. Installation and Setup 3. Getting Started with RiscFree* IDE 4. Debug Setup for Nios® V Processor System 5. Debug Setup for Arm* Hard Processor System 6. Debugging with RiscFree* IDE 7. Ashling RiscFree* Integrated Development Environment (IDE) for Intel® FPGAs User Guide Archives 8. Document Revision History for the Ashling RiscFree* Integrated Development Environment (IDE) for Intel® FPGAs User Guide A. Appendix
1. About the RiscFree* IDE x
1.1. Supported Devices 1.2. Intel® Quartus® Prime Software Support
2. Installation and Setup x
2.1. Bundled Installation with the Intel® Quartus® Prime Software 2.2. Standalone Installation
2.2. Standalone Installation x
2.2.1. Standalone Installation with Supported Intel® Quartus® Prime Software 2.2.2. Standalone Installation with the Intel® Quartus® Prime Programmer and Tools
3. Getting Started with RiscFree* IDE x
3.1. Graphical User Interface 3.2. Command Line Interface
4. Debug Setup for Nios® V Processor System x
4.1. Importing Nios® V Project 4.2. Building Nios® V Project 4.3. Setting Debug Configurations and Downloading Nios® V Project Using RiscFree* IDE
5. Debug Setup for Arm* Hard Processor System x
5.1. Pre-requisite for Debugging Arm* HPS Project 5.2. Importing Arm* HPS Project 5.3. Setting Debug Configurations and Downloading Arm* HPS Project Using RiscFree* IDE
6. Debugging with RiscFree* IDE x
6.1. Debug Features in RiscFree* IDE 6.2. Processor System Debug 6.3. Heterogeneous Multicore Debug 6.4. Debugging µC/OS-II Application
6.1. Debug Features in RiscFree* IDE x
6.1.1. Viewing Global Variables 6.1.2. Launching Memory Browser 6.1.3. Debugger Console 6.1.4. Specifying the SVD File 6.1.5. Breakpoint Settings 6.1.6. JTAG UART Output Terminal
6.2. Processor System Debug x
6.2.1. GUI for Debugging
6.3. Heterogeneous Multicore Debug x
6.3.1. Importing Nios® V and Arm* HPS Projects 6.3.2. Setting Core Configuration
A. Appendix x
A.1. Optional Toolchain Configuration A.2. Performing External Tools Configuration A.3. Help Content A.4. Open-Source Components in RiscFree* IDE
A.1. Optional Toolchain Configuration x
A.1.1. Toolchain for Application and BSP A.1.2. Toolchain for Arm* Processor A.1.3. Modifying Toolchain Configuration
1. About the RiscFree* IDE
2. Installation and Setup
3. Getting Started with RiscFree* IDE
4. Debug Setup for Nios® V Processor System
5. Debug Setup for Arm* Hard Processor System
6. Debugging with RiscFree* IDE
7. Ashling RiscFree* Integrated Development Environment (IDE) for Intel® FPGAs User Guide Archives
8. Document Revision History for the Ashling RiscFree* Integrated Development Environment (IDE) for Intel® FPGAs User Guide
A. Appendix

6.3.2. Setting Core Configuration

To set the core configuration, follow these steps:

  1. Right click project directory (either HPS or Nios® V application) and select Debug > Debug Configurations.
  2. Select Ashling Heterogenous Multicore Debugging > cortex-a53-sum.elf.
  3. Under the Device tab, set these settings:
    • Debug probe: 1 (USB-Blaster II)
    • JTAG/SWD frequency: 16 MHz
    • Transport type: JTAG
    • Target device: Agilex
  4. Under Core Configuration, select Cortex-A53 and Nios V/m.
    Figure 18. List of Available Cores for the Selected Target Device in RiscFree* IDE
  5. Set the core specific configuration for each core under the Debugger tab.
  6. Specify the .elf file for each core under the Target Application tab. In this example, the target applications are added as nios-v-sum.elf for Nios V/m core and cortex-a53-sum.elf for Cortex-A53 core.
    Note: You can specify multiple .elf file for a single core.
    Figure 19. Target Application Tab Settings
  7. Set the breakpoint at a specific function under the Startup tab. This debug example uses the default settings.
    Figure 20. Startup Tab Settings
  8. Based on the OS you use, configure the OS Awareness settings as follows:
    • Intel® HAL: No OS Awareness configuration is required.
    • µC/OS-II: Under the OS Awareness tab, turn on Enable OS Aware Debugging, and select OS: µC/OS and Version: II.
    Figure 21. Enabling µC/OS-II Aware Debugging in Heterogeneous Debugging
  9. Click Debug when all configuration is complete. All cores selected for debug are launched.
    Figure 22. Heterogeneous Multicore Debug View in RiscFree* IDE
  10. To debug two cores simultaneously, go to Window > Show View > Registers. Then, make a copy of the existing debug view using the Open new View icon.
    Figure 23. Register Window
  11. In the Heterogenous Multicore Debug View pane, select Thread #1 [TAP 3 Core 0 (Cortex-A53)]. Pin one copy of the debug view to Arm processor using the Pin to Debug Context icon.
    Figure 24. Arm Processor (Core 0) Register View
  12. In the Heterogenous Multicore Debug View pane, select Thread #1 [TAP 2 (Nios V/m Hart 0)]. Pin second copy of the debug view to Nios V processor using the Pin to Debug Context icon.
    Figure 25. Nios V Processor (Core 4) Register View
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