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1. About the RiscFree* IDE
2. Installation and Setup
3. Getting Started with RiscFree* IDE
4. Debug Setup for Nios® V Processor System
5. Debug Setup for Arm* Hard Processor System
6. Debugging with RiscFree* IDE
7. Ashling RiscFree* Integrated Development Environment (IDE) for Intel® FPGAs User Guide Archives
8. Document Revision History for the Ashling RiscFree* Integrated Development Environment (IDE) for Intel® FPGAs User Guide
A. Appendix
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6.1.2. Launching Memory Browser
RiscFree* IDE supports memory browser.
To launch the memory browser, follow these steps:
- Go to Window > Show View > Memory Browser.
- View the target memory in the memory browser.
Figure 13. Memory Browser showing Target Memory