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1. About the RiscFree* IDE
2. Installation and Setup
3. Getting Started with RiscFree* IDE
4. Debug Setup for Nios® V Processor System
5. Debug Setup for Arm* Hard Processor System
6. Debugging with RiscFree* IDE
7. Ashling RiscFree* Integrated Development Environment (IDE) for Intel® FPGAs User Guide Archives
8. Document Revision History for the Ashling RiscFree* Integrated Development Environment (IDE) for Intel® FPGAs User Guide
A. Appendix
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5. Debug Setup for Arm* Hard Processor System
This section provides guidance on debugging Arm* HPS core using the RiscFree* IDE debugging tool and accessing the hardware modules (for example, peripherals) that are instantiated in the RiscFree* IDE FPGA design. This tutorial is based on the Intel® FPGA example design from Ashling.
Note: RiscFree* IDE supports Arm* HPS standalone debug.