Ashling* RiscFree* Integrated Development Environment (IDE) for Intel® FPGAs User Guide

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ID 730783
Date 10/31/2022
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Document Table of Contents
Document Table of Contents x
1. About the RiscFree* IDE 2. Installation and Setup 3. Getting Started with RiscFree* IDE 4. Debug Setup for Nios® V Processor System 5. Debug Setup for Arm* Hard Processor System 6. Debugging with RiscFree* IDE 7. Ashling RiscFree* Integrated Development Environment (IDE) for Intel® FPGAs User Guide Archives 8. Document Revision History for the Ashling RiscFree* Integrated Development Environment (IDE) for Intel® FPGAs User Guide A. Appendix
1. About the RiscFree* IDE x
1.1. Supported Devices 1.2. Intel® Quartus® Prime Software Support
2. Installation and Setup x
2.1. Bundled Installation with the Intel® Quartus® Prime Software 2.2. Standalone Installation
2.2. Standalone Installation x
2.2.1. Standalone Installation with Supported Intel® Quartus® Prime Software 2.2.2. Standalone Installation with the Intel® Quartus® Prime Programmer and Tools
3. Getting Started with RiscFree* IDE x
3.1. Graphical User Interface 3.2. Command Line Interface
4. Debug Setup for Nios® V Processor System x
4.1. Importing Nios® V Project 4.2. Building Nios® V Project 4.3. Setting Debug Configurations and Downloading Nios® V Project Using RiscFree* IDE
5. Debug Setup for Arm* Hard Processor System x
5.1. Pre-requisite for Debugging Arm* HPS Project 5.2. Importing Arm* HPS Project 5.3. Setting Debug Configurations and Downloading Arm* HPS Project Using RiscFree* IDE
6. Debugging with RiscFree* IDE x
6.1. Debug Features in RiscFree* IDE 6.2. Processor System Debug 6.3. Heterogeneous Multicore Debug 6.4. Debugging µC/OS-II Application
6.1. Debug Features in RiscFree* IDE x
6.1.1. Viewing Global Variables 6.1.2. Launching Memory Browser 6.1.3. Debugger Console 6.1.4. Specifying the SVD File 6.1.5. Breakpoint Settings 6.1.6. JTAG UART Output Terminal
6.2. Processor System Debug x
6.2.1. GUI for Debugging
6.3. Heterogeneous Multicore Debug x
6.3.1. Importing Nios® V and Arm* HPS Projects 6.3.2. Setting Core Configuration
A. Appendix x
A.1. Optional Toolchain Configuration A.2. Performing External Tools Configuration A.3. Help Content A.4. Open-Source Components in RiscFree* IDE
A.1. Optional Toolchain Configuration x
A.1.1. Toolchain for Application and BSP A.1.2. Toolchain for Arm* Processor A.1.3. Modifying Toolchain Configuration
1. About the RiscFree* IDE
2. Installation and Setup
3. Getting Started with RiscFree* IDE
4. Debug Setup for Nios® V Processor System
5. Debug Setup for Arm* Hard Processor System
6. Debugging with RiscFree* IDE
7. Ashling RiscFree* Integrated Development Environment (IDE) for Intel® FPGAs User Guide Archives
8. Document Revision History for the Ashling RiscFree* Integrated Development Environment (IDE) for Intel® FPGAs User Guide
A. Appendix

5.3. Setting Debug Configurations and Downloading Arm* HPS Project Using RiscFree* IDE

To debug the project, follow these steps:

  1. Right click on the project directory and select Debug > Debug Configurations.
  2. Select Ashling Arm Hardware Debugging > cortex-a53-sum. Ensure the Project and C/C++ Application match with your project name and your project .elf file respectively.
  3. Under the Debugger tab, set these settings:
    • Debug probe: 1 (USB-Blaster II) — Select the connected device
    • Transport type: JTAG
    • JTAG/SWD frequency: 16 MHz
    • Target device: Agilex
    • Core selection: Can select any core between 0 to 3
    Figure 10. Debugger Settings for Intel® Agilex™ Arm* Cortex* -A53 Core
    Note: The default settings for the current example design in the RiscFree* IDE are configured based on Intel® Agilex™ device.
    Note:

    If you are using a different Arm* architecture, select the Arm* GNU debugger (GDB) (select GDB Client Setup > Executable name) manually.

    • 64-bit ELFs: ${eclipse_home}/../toolchain/Arm/aarch64-none-elf/bin/aarch64-none-elf-gdb.exe
    • 32-bit ELFs: ${eclipse_home}/../toolchain/Arm/arm-none-eabi/bin/arm-none-eabi-gdb.exe
  4. Click Debug. RiscFree* IDE downloads the program to the target and you can find the console prints as shown in the following diagram.
    Figure 11.  RiscFree* IDE after Program is Downloaded and System is Ready for Debug
  5. Refer to the Debugging with RiscFree* IDE section for further debugging.
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