Visible to Intel only — GUID: bnt1652884762926
Ixiasoft
1. About the RiscFree* IDE
2. Getting Started with the Ashling* RiscFree* IDE for Intel® FPGAs
3. Using Ashling* RiscFree* IDE for Intel® FPGAs with Nios® V Processor System
4. Using Ashling* RiscFree* IDE for Intel® FPGAs with Arm* Hard Processor System
5. Debugging Features with RiscFree* IDE for Intel® FPGAs
6. Debugging with Command-Line Interface
7. Ashling RiscFree* Integrated Development Environment (IDE) for Intel® FPGAs User Guide Archives
8. Document Revision History for the Ashling RiscFree* Integrated Development Environment (IDE) for Intel® FPGAs User Guide
A. Appendix
3.1. Importing Nios® V Processor Project
3.2. Building Nios® V Processor Project
3.3. Setting Run Configuration to Download Nios® V Processor Project
3.4. Setting Debug Configuration to Debug Nios® V Processor Project
3.5. Setting Debug Configuration to Debug a Booting Nios® V Processor Project
3.6. Debugging Tools
5.1. Debug Features in RiscFree* IDE
5.2. Processor System Debug
5.3. Heterogeneous Multicore Debug
5.4. Debugging µC/OS-II Application
5.5. Debugging FreeRTOS Application
5.6. Debugging Zephyr Application
5.7. Arm* HPS On-Chip Trace
5.8. Debugging the Arm* Linux Kernel
5.9. Debugging Target Software in an Intel® Simics Simulator Session
Visible to Intel only — GUID: bnt1652884762926
Ixiasoft
5.3.2. Setting Core Configuration
To set the core configuration, follow these steps:
- Right click project directory (either HPS or Nios® V application) and select Debug > Debug Configurations.
- Select Ashling Heterogenous Multicore Debugging > cortex-a53-sum.elf.
- Under the Device tab, set these settings:
- Debug probe: Agilex SI/SoC Dev Kit
- JTAG/SWD frequency: 16 MHz
- Transport type: JTAG
- Click the Auto-detect Scan Chain to list out all the available cores.
- Under Core Configuration, select Cortex-A53 and Nios V/m.
Figure 43. List of Available Cores for the Selected Target Device in RiscFree* IDE
- Set the core specific configuration for each core under the Debugger tab.
- Specify the .elf file for each core under the Target Application tab. In this example, the target applications are added as nios-v-sum.elf for Nios V/m core and cortex-a53-sum.elf for Cortex-A53 core.
Note: You can specify multiple .elf file for a single core.Figure 44. Target Application Tab Settings
- Set the breakpoint at a specific function under the Startup tab. This debug example uses the default settings.
Figure 45. Startup Tab Settings
- Based on the OS you use, configure the OS Awareness settings as follows:
- Intel® HAL: No OS Awareness configuration is required.
- Other OS: Under the OS Awareness tab, turn on Enable OS Aware Debugging, and select the OS as listed below:
- µC/OS and Version: II
- FreeRTOS and Version: 10.4.1
- Zephyr and Version: 3.1.0
Figure 46. Enabling OS Aware Debugging in Heterogeneous Debugging - Click Debug when all configuration is complete. All cores selected for debug are launched.
Figure 47. Heterogeneous Multicore Debug View in RiscFree* IDE
- To debug two cores simultaneously, go to Window > Show View > Registers. Then, make a copy of the existing debug view using the Open new View icon.
Figure 48. Register Window
- In the Heterogenous Multicore Debug View pane, select Thread #1 [TAP 3 Core 0 (Cortex-A53)]. Pin one copy of the debug view to Arm processor using the Pin to Debug Context icon.
Figure 49. Arm Processor (Core 0) Register View
- In the Heterogenous Multicore Debug View pane, select Thread #1 [TAP 2 (Nios V/m Hart 0)]. Pin second copy of the debug view to Nios V processor using the Pin to Debug Context icon.
Figure 50. Nios V Processor (Core 4) Register View