Nios® V Embedded Processor Design Handbook

ID 726952
Date 7/08/2024
Public
Document Table of Contents

8.2.7. Operating the Example Design

To display the application messages, the example design utilizes the JTAG UART Intel FPGA IP. You can begin the display message by using the following command:

juart-terminal
Figure 138. Output Result from PE1
Figure 139. Output Result from PE2