Nios® V Embedded Processor Design Handbook

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ID 726952
Date 7/08/2024
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Document Table of Contents
Document Table of Contents x
1. About the Nios® V Embedded Processor 2. Nios® V Processor Hardware System Design with Quartus® Prime Software and Platform Designer 3. Nios® V Processor Software System Design 4. Nios® V Processor Configuration and Booting Solutions 5. Nios® V Processor - Using the MicroC/TCP-IP Stack 6. Nios® V Processor Debugging, Verifying, and Simulating 7. Nios® V Processor — Remote System Update 8. Nios® V Processor — Using Custom Instruction 9. Nios® V Embedded Processor Design Handbook Archives 10. Document Revision History for the Nios® V Embedded Processor Design Handbook
1. About the Nios® V Embedded Processor x
1.1. Intel® FPGA and Embedded Processors Overview 1.2. Quartus® Prime Software Support 1.3. Nios® V Processor Licensing 1.4. Embedded System Design
2. Nios® V Processor Hardware System Design with Quartus® Prime Software and Platform Designer x
2.1. Creating Nios® V Processor System Design with Platform Designer 2.2. Integrating Platform Designer System into the Quartus® Prime Project 2.3. Designing a Nios® V Processor Memory System 2.4. Clocks and Resets Best Practices 2.5. Assigning a Default Agent 2.6. Assigning a UART Agent for Printing 2.7. JTAG Signals
2.1. Creating Nios® V Processor System Design with Platform Designer x
2.1.1. Instantiating Nios® V Processor Intel® FPGA IP 2.1.2. Defining System Component Design 2.1.3. Specifying Base Addresses and Interrupt Request Priorities
2.1.1. Instantiating Nios® V Processor Intel® FPGA IP x
2.1.1.1. Instantiating Nios® V/c Compact Microcontroller Intel® FPGA IP 2.1.1.2. Instantiating Nios® V/m Microcontroller Intel® FPGA IP 2.1.1.3. Instantiating Nios® V/g General Purpose Processor Intel® FPGA IP
2.1.1.1. Instantiating Nios® V/c Compact Microcontroller Intel® FPGA IP x
2.1.1.1.1. Use Reset Request Tab 2.1.1.1.2. Vectors Tab 2.1.1.1.3. ECC Tab
2.1.1.2. Instantiating Nios® V/m Microcontroller Intel® FPGA IP x
2.1.1.2.1. Debug Tab 2.1.1.2.2. Use Reset Request Tab 2.1.1.2.3. Vectors Tab 2.1.1.2.4. CPU Architecture 2.1.1.2.5. ECC Tab
2.1.1.3. Instantiating Nios® V/g General Purpose Processor Intel® FPGA IP x
2.1.1.3.1. Debug Tab 2.1.1.3.2. Use Reset Request Tab 2.1.1.3.3. Vectors Tab 2.1.1.3.4. Memory Configurations Tab 2.1.1.3.5. Custom Instruction Tab 2.1.1.3.6. CPU Architecture 2.1.1.3.7. ECC Tab
2.2. Integrating Platform Designer System into the Quartus® Prime Project x
2.2.1. Instantiating the Nios® V Processor System Module in the Quartus® Prime Project 2.2.2. Connecting Signals and Assigning Physical Pin Locations 2.2.3. Constraining the Intel FPGA Design
2.3. Designing a Nios® V Processor Memory System x
2.3.1. Volatile Memory 2.3.2. Non-Volatile Memory 2.3.3. On-Chip Memory Configuration – RAM or ROM 2.3.4. Caches 2.3.5. Tightly Coupled Memory
2.4. Clocks and Resets Best Practices x
2.4.1. System Clock 2.4.2. Reset Request Interface 2.4.3. Reset Release IP
2.4.2. Reset Request Interface x
2.4.2.1. Typical Use Cases
2.6. Assigning a UART Agent for Printing x
2.6.1. Preventing Stalls by the JTAG UART
3. Nios® V Processor Software System Design x
3.1. Nios V Processor Software Development Flow 3.2. Intel FPGA Embedded Development Tools
3.1. Nios V Processor Software Development Flow x
3.1.1. Board Support Package Project 3.1.2. Application Project
3.2. Intel FPGA Embedded Development Tools x
3.2.1. Nios® V Processor Board Support Package Editor 3.2.2. RiscFree* IDE for Intel FPGAs 3.2.3. Nios V Utilities Tools 3.2.4. File Format Conversion Tools 3.2.5. Other Utilities Tools
4. Nios® V Processor Configuration and Booting Solutions x
4.1. Introduction 4.2. Linking Applications 4.3. Nios® V Processor Booting Methods 4.4. Introduction to Nios® V Processor Booting Methods 4.5. Nios® V Processor Booting from Configuration QSPI Flash 4.6. Nios® V Processor Booting from On-Chip Memory (OCRAM) 4.7. Nios® V Processor Booting from Tightly Coupled Memory (TCM) 4.8. Summary of Nios® V Processor Vector Configuration and BSP Settings
4.2. Linking Applications x
4.2.1. Linking Behavior
4.2.1. Linking Behavior x
4.2.1.1. Default BSP Linking 4.2.1.2. Configurable BSP Linking
4.4. Introduction to Nios® V Processor Booting Methods x
4.4.1. Nios® V Processor Application Execute-In-Place from Boot Flash 4.4.2. Nios® V Processor Application Copied from Boot Flash to RAM Using Boot Copier 4.4.3. Nios® V Processor Application Execute-In-Place from OCRAM 4.4.4. Nios® V Processor Application Execute-In-Place from TCM
4.4.1. Nios® V Processor Application Execute-In-Place from Boot Flash x
4.4.1.1. alt_load()
4.4.2. Nios® V Processor Application Copied from Boot Flash to RAM Using Boot Copier x
4.4.2.1. Nios® V Processor Bootloader via Generic Serial Flash Interface 4.4.2.2. Nios® V Processor Bootloader via Secure Device Manager
4.5. Nios® V Processor Booting from Configuration QSPI Flash x
4.5.1. Nios V Processor Design, Configuration and Boot Flow (Control Block-based Device) 4.5.2. Nios V Processor Design, Configuration and Boot Flow (SDM-based Devices)
4.5.1. Nios V Processor Design, Configuration and Boot Flow (Control Block-based Device) x
4.5.1.1. Nios® V Processor Application Executes-In-Place from Configuration QSPI Flash 4.5.1.2. Nios® V Processor Application Copied from Configuration QSPI Flash to RAM Using Boot Copier (Bootloader via GSFI) 4.5.1.3. Bootloader via GSFI Example Design
4.5.1.1. Nios® V Processor Application Executes-In-Place from Configuration QSPI Flash x
4.5.1.1.1. Hardware Design Flow 4.5.1.1.2. Software Design Flow 4.5.1.1.3. Programming Files Generation 4.5.1.1.4. QSPI Flash Programming
4.5.1.2. Nios® V Processor Application Copied from Configuration QSPI Flash to RAM Using Boot Copier (Bootloader via GSFI) x
4.5.1.2.1. Hardware Design Flow 4.5.1.2.2. Software Design Flow 4.5.1.2.3. Programming Files Generation 4.5.1.2.4. QSPI Flash Programming
4.5.2. Nios V Processor Design, Configuration and Boot Flow (SDM-based Devices) x
4.5.2.1. Nios® V Processor Application Copied from Configuration QSPI Flash to RAM Using Boot Copier (Bootloader via SDM) 4.5.2.2. Bootloader via SDM Example Design
4.5.2.1. Nios® V Processor Application Copied from Configuration QSPI Flash to RAM Using Boot Copier (Bootloader via SDM) x
4.5.2.1.1. Hardware Design Flow 4.5.2.1.2. Software Design Flow 4.5.2.1.3. Software Design Flow (Bootloader via SDM Project) 4.5.2.1.4. Software Design Flow (User Application Project) 4.5.2.1.5. Programming Files Generation 4.5.2.1.6. QSPI Flash Programming SDM
4.6. Nios® V Processor Booting from On-Chip Memory (OCRAM) x
4.6.1. Nios® V Processor Application Executes in-place from OCRAM
4.6.1. Nios® V Processor Application Executes in-place from OCRAM x
4.6.1.1. Hardware Design Flow 4.6.1.2. Software Design Flow 4.6.1.3. Programming
4.7. Nios® V Processor Booting from Tightly Coupled Memory (TCM) x
4.7.1. Nios® V Processor Application Executes in-place from TCM
4.7.1. Nios® V Processor Application Executes in-place from TCM x
4.7.1.1. Hardware Design Flow 4.7.1.2. Software Design Flow 4.7.1.3. Programming
5. Nios® V Processor - Using the MicroC/TCP-IP Stack x
5.1. Introduction 5.2. Software Architecture 5.3. Support and Licensing 5.4. MicroC/TCP-IP Example Designs 5.5. Development Flow 5.6. Operating the Example Designs 5.7. Optional Configuration 5.8. MicroC/TCP-IP Simple Socket Server Concepts
5.4. MicroC/TCP-IP Example Designs x
5.4.1. Hardware and Software Requirements 5.4.2. Overview 5.4.3. Acquiring the Example Design Files 5.4.4. Hardware Design Files 5.4.5. Software Design Files
5.4.5. Software Design Files x
5.4.5.1. MicroC/TCP-IP IPerf Example Design 5.4.5.2. MicroC/TCP-IP Simple Socket Server Example Design
5.5. Development Flow x
5.5.1. Hardware Development Flow 5.5.2. Software Development Flow 5.5.3. Device Programming
5.5.2. Software Development Flow x
5.5.2.1. Creating a BSP project 5.5.2.2. Configuring the BSP 5.5.2.3. Creating an Application Project 5.5.2.4. Building the Application Project
5.6. Operating the Example Designs x
5.6.1. Operating the MicroC/TCP-IP IPerf 5.6.2. Operating the MicroC/TCP-IP Simple Socket Server
5.7. Optional Configuration x
5.7.1. Configuring Hardware Name 5.7.2. Configuring MAC and IP Addresses 5.7.3. Configuring MicroC/TCP-IP Initialization 5.7.4. Configuring iPerf Server Auto-Initialization
5.7.3. Configuring MicroC/TCP-IP Initialization x
5.7.3.1. Network Task Configuration 5.7.3.2. Network Interface Configuration
5.8. MicroC/TCP-IP Simple Socket Server Concepts x
5.8.1. MicroC/OS-II Resources 5.8.2. Error Handling 5.8.3. MicroC/TCP-IP Stack Default Configuration
6. Nios® V Processor Debugging, Verifying, and Simulating x
6.1. Debugging Nios® V/c Processor 6.2. Debugging Nios® V Processor Hardware Designs 6.3. Debugging Nios® V Processor Software Designs 6.4. Debugging Tools 6.5. Additional Embedded Design Considerations 6.6. Simulating Nios® V Processor Designs
6.1. Debugging Nios® V/c Processor x
6.1.1. Pilot System with Non-pipelined Nios V/m Processor 6.1.2. printf() Debugging
6.2. Debugging Nios® V Processor Hardware Designs x
6.2.1. JTAG Server 6.2.2. System Console 6.2.3. Signal Tap Logic Analyzer 6.2.4. In-System Sources and Probes
6.2.2. System Console x
6.2.2.1. JTAG to Avalon® Host Bridge Core
6.2.3. Signal Tap Logic Analyzer x
6.2.3.1. Hardware and Software Requirements 6.2.3.2. Setting Up Signal Tap Logic Analyzer 6.2.3.3. Running the Capture Session 6.2.3.4. Analyzing Results
6.2.3.2. Setting Up Signal Tap Logic Analyzer x
6.2.3.2.1. Enabling Signal Tap Logic Analyzer 6.2.3.2.2. Adding Signals for Monitoring and Debugging 6.2.3.2.3. Specifying Trigger Conditions 6.2.3.2.4. Assigning the Acquisition Clock, Sample Depth, and Memory Type, and Buffer Acquisition Mode 6.2.3.2.5. Compiling the Design and Programming the Target Device
6.2.3.2.3. Specifying Trigger Conditions x
6.2.3.2.3.1. Basic Trigger Conditions 6.2.3.2.3.2. Power-Up Trigger Conditions 6.2.3.2.3.3. Other Trigger Conditions 6.2.3.2.3.4. No Trigger Conditions
6.2.3.3. Running the Capture Session x
6.2.3.3.1. Performing Data Capture with Ashling* RiscFree* IDE for Intel® FPGAs 6.2.3.3.2. Performing Data Capture Without Software Download
6.2.3.4. Analyzing Results x
6.2.3.4.1. Viewing Data 6.2.3.4.2. Correlating Trace Data to Software ELF 6.2.3.4.3. Saving and Converting Captured Data
6.3. Debugging Nios® V Processor Software Designs x
6.3.1. Ashling* RiscFree* IDE for Intel® FPGAs 6.3.2. OpenOCD 6.3.3. Objdump File 6.3.4. Show Make Commands
6.5. Additional Embedded Design Considerations x
6.5.1. JTAG Signal Integrity 6.5.2. Additional Memory Space for System Prototyping
6.6. Simulating Nios® V Processor Designs x
6.6.1. Prerequisites 6.6.2. Setting Up and Generating Your Simulation Environment in Platform Designer 6.6.3. Creating Nios V Processor Software 6.6.4. Generating Memory Initialization File 6.6.5. Generating System Simulation Files 6.6.6. Running Simulation in the QuestaSim Simulator Using Command Line
6.6.2. Setting Up and Generating Your Simulation Environment in Platform Designer x
6.6.2.1. Using IP and Platform Designer Simulation Setup Scripts
6.6.3. Creating Nios V Processor Software x
6.6.3.1. Generating the Board Support Package 6.6.3.2. Generating the Application Project File 6.6.3.3. Building the Application Project
7. Nios® V Processor — Remote System Update x
7.1. Overview 7.2. Quartus® Prime Pro Edition Software and Tool Support 7.3. Nios® V Processor RSU Quick Start Guide in SDM-based Devices
7.2. Quartus® Prime Pro Edition Software and Tool Support x
7.2.1. Intel® Quartus® Prime Pro Edition Software 7.2.2. Programming File Generator
7.2.1. Intel® Quartus® Prime Pro Edition Software x
7.2.1.1. Setting Max Retry Parameter 7.2.1.2. Selecting Factory Load Pin
7.2.2. Programming File Generator x
7.2.2.1. Programming File Generator File Types 7.2.2.2. Bitswap Option 7.2.2.3. Quartus® Prime Programmer 7.2.2.4. Supported QSPI Flash Devices
7.3. Nios® V Processor RSU Quick Start Guide in SDM-based Devices x
7.3.1. Individual Factory, Application, and Update Images 7.3.2. Hardware Design Flow 7.3.3. Software Design Flow 7.3.4. Individual Images Generation 7.3.5. Remote System Update Image Files Generation 7.3.6. QSPI Flash Programming 7.3.7. Operating the RSU Client API
7.3.2. Hardware Design Flow x
7.3.2.1. Create a Platform Designer System 7.3.2.2. Quartus® Prime Software Settings
7.3.3. Software Design Flow x
7.3.3.1. Generating the ZLIB libraries 7.3.3.2. Creating a Board Support Package Project 7.3.3.3. Configuring and Generating the BSP Project 7.3.3.4. Creating Multiple Application Projects 7.3.3.5. Building the Application Projects 7.3.3.6. Generating HEX Files
7.3.5. Remote System Update Image Files Generation x
7.3.5.1. Generating Initial RSU Image Using SOF file 7.3.5.2. Generating an Application Update Image 7.3.5.3. Generating a Factory Update Flash Image
7.3.6. QSPI Flash Programming x
7.3.6.1. Programming the Initial RSU Image 7.3.6.2. Programming the Update Images
7.3.7. Operating the RSU Client API x
7.3.7.1. Trigger Reconfiguration Menu with Selected Image 7.3.7.2. Updating an Application Image 7.3.7.3. Updating the Factory Image
8. Nios® V Processor — Using Custom Instruction x
8.1. Introduction 8.2. Unimplemented Instruction Example Design 8.3. Hardware Acceleration Example Design
8.2. Unimplemented Instruction Example Design x
8.2.1. Hardware and Software Requirements 8.2.2. Overview 8.2.3. Acquiring the Example Design File 8.2.4. Hardware Design Files 8.2.5. Software Design Files 8.2.6. Development Flow 8.2.7. Operating the Example Design
8.2.6. Development Flow x
8.2.6.1. Hardware Development Flow 8.2.6.2. Software Development Flow 8.2.6.3. Device Programming
8.3. Hardware Acceleration Example Design x
8.3.1. Hardware and Software Requirements 8.3.2. Overview 8.3.3. Acquiring the Example Design File 8.3.4. Hardware Design Files 8.3.5. Software Design Files 8.3.6. Development Flow 8.3.7. Operating the Example Design
8.3.6. Development Flow x
8.3.6.1. Hardware Development Flow 8.3.6.2. Software Development Flow 8.3.6.3. Device Programming
1. About the Nios® V Embedded Processor
2. Nios® V Processor Hardware System Design with Quartus® Prime Software and Platform Designer
3. Nios® V Processor Software System Design
4. Nios® V Processor Configuration and Booting Solutions
5. Nios® V Processor - Using the MicroC/TCP-IP Stack
6. Nios® V Processor Debugging, Verifying, and Simulating
7. Nios® V Processor — Remote System Update
8. Nios® V Processor — Using Custom Instruction
9. Nios® V Embedded Processor Design Handbook Archives
10. Document Revision History for the Nios® V Embedded Processor Design Handbook

10. Document Revision History for the Nios® V Embedded Processor Design Handbook

Document Version Quartus® Prime Version Changes
2024.07.08 24.2
  • Removed the mention of Eclipse CDT for Embedded C/C++ Developers throughout the document.
  • Replaced the mention of SDM Bootloader to Bootloader via SDM.
  • Replaced the mention of GSFI Bootloader to Bootloader via GSFI.
  • Added subtopics to the topic Signal Tap Logic Analyzer.
2024.05.13 24.1
  • Removed the topic Nios® V Processor Quick Start Guide. Added a link to AN 985: Nios® V Processor Tutorial..
  • Updated the topics in Instantiating Nios® V/m Microcontroller
    • Updated the figures in Instantiating Nios® V/m Microcontroller Intel FPGA IP.
    • Updated the table CPU Architecture with mhartid CSR value.
  • Updated the topics in Instantiating Nios® V/g Microcontroller
    • Updated the figures in Instantiating Nios® V/g Microcontroller Intel FPGA IP.
    • Updated the table CPU Architecture with mhartid CSR value.
    • Added new topics:
      • Caches
      • Tightly Coupled Memory
      • System Clock
      • Reset Release IP
      • Assigning a UART Agent for Printing
      • Preventing Stalls by the JTAG UART
      • JTAG Signals
  • Updated the section Nios V Processor Application Executes-in-place from TCM
    • Updated the figures and steps in Hardware Design Flow
    • Added new steps in Software Design Flow.
  • Updated the topics in Debugging Nios V/c Processor:
    • Pilot System with Non-pipelined Nios V/m Processor
    • printf() Debugging
    • Added
      • Debugging Nios® V Processor Hardware Designs
      • JTAG Server
      • System Console
      • JTAG to Avalon Host Bridge Core
      • Signal Tap Logic Analyzer
      • In-System Sources and Probes
      • Ashling* RiscFree* IDE for Intel FPGA
  • Updated the topics in Nios V Processor — Remote System Update
    • Updated the steps in Configuring and Generating the BSP Project.
    • Updated the steps in Creating Multiple Applications.
2023.12.04 23.4
  • Updated the note to refer to AN 980: Nios V Processor Intel Quartus Prime Software Support throughout the document.
  • Updated the titles and figures in Instantiating Nios V Processor Intel FPGA IP for the following Nios® V processor cores:
    • Nios® V/c Compact Microcontroller Processor Intel® FPGA IP
    • Nios® V/m Microcontroller Intel® FPGA IP
    • Nios® V/g General Purpose Processor Intel® FPGA IP
  • Updated the table: CPU Architecture to remove atomic extensions.
  • Added the command for Quartus® Prime Standard Edition version in the following topics:
    • Table: GUI Tools and Command-line Tools Tasks Summary.
    • Topic: Generating the Board Support Package in Creating Nios V Processor Software.
  • Edited the title for Example Design on Unimplemented Instruction (Custom Instruction Design on Nios® V/g processor) to Unimplemented Instruction Example Design.
  • Added topic Hardware Acceleration Example Designs.
2023.10.02 23.3
  • Added new topics based on new addition Nios® V/c processor:
    • Nios® V Processor Licensing
    • Instantiating Nios® V Processor IP Core
    • Instantiating Nios® V/c Processor Intel® FPGA IP
    • Instantiating Nios® V/m Processor Intel® FPGA IP
    • Instantiating Nios® V/g Processor Intel® FPGA IP
    • Debugging Nios® V/c Processor
    • Steps to Debug Nios® V/c Processor
  • Updated Nios® V Processor Configuration and Booting Solutions with TCM related in the following topics:
    • Nios® V Processor Booting Methods
    • Added Nios® V Processor Application Execute-In-Place from TCM
    • Added Nios® V Processor Booting from Tightly Coupled Memory (TCM)
    • Summary of Nios® V Processor Vector Configuration and BSP Settings
  • Updated the mention of Nios® V/m to Nios® V in related topics with the release of Nios® V/g and Nios® V/c processors.
2023.09.01 23.2
  • Updated Software Design Flow in Processor Application Executes-In-Place from Configuration QSPI Flash:
    • Updated figures:
      • Linker Region Settings When Exceptions is set to OCRAM / External RAM.
      • Linker Region Settings When Exceptions is set to QSPI Flash .
    • Added steps to disable gsfi driver.
  • Added new section: Nios® V Processor RSU Quick Start Guide in SDM-based Devices.
  • Updated figure Nios® V Processor System Design Flow in the topic Embedded System Design.
2023.05.26 23.1
  • Added links to AN 980: Nios® V Processor Quartus® Prime Software Support.
  • Added a new section: Nios® V Processor — Using Custom Instruction.
2023.04.10 23.1
  • Added new topics:
    • Caches and Peripheral Regions Tab
    • Custom Instruction Tab
  • Added table GSFI Bootloader for Nios V Processor Core in the topic GSFI Bootloader.
  • Added a new step in the topic Generating HEX File from the section Processor Application Copied from Configuration QSPI Flash to RAM Using Boot Copier (GSFI Bootloader).
  • Updated product family name to " Intel Agilex® 7".
Document Version Quartus® Prime Version IP Version Changes
2023.02.14 22.4 22.4.0
  • Edited topic Intel® Quartus® Prime Software Support.
  • Edited topic Nios V/m Processor Example Design.
  • Added a note in the following topics to refer to the topic Intel® Quartus® Prime Software Support
    • Generating the Board Support Package using the BSP Editor GUI
    • Nios V Board Support Package Editor
    • Software Design Flow
    • Creating a BSP project
  • Updated the following topics to align with the design store migration steps:
    • Generating the Application Project File
    • GSFI Bootloader Example Design
    • SDM Bootloader Example Design
    • MicroC/TCP-IP Example Designs: Overview
    • Acquiring the Example Design Files
    • Creating an Application Project
    • Device Programming
    • Optional Configuration
  • Removed the following topics:
    • Generating the Example Design Through Graphical User Interface
    • Generating the Nios V/m Processor Example Design Using the Command Line Interface
    • Generate Nios V processor example design from Platform Designer
    • HEX File Generation
2022.10.31 22.1std 1.0.0
  • Updated references from Intel® Quartus® Prime Pro Edition to Intel® Quartus® Prime to indicate support for both Pro and Standard Edition.
  • Added new topic: Intel® Quartus® Prime Software Support.
2022.10.25 22.3 22.3.0
  • Added new section: Nios V Processor — Remote System Update.
2022.09.26 22.3 22.3.0
  • Updated Configure Nios V Processor Parameters
    • Edited Debug Tab
    • Added Use Reset Request Tab
    • Edited Vectors Tab. Removed Exception Agent and Exception Offset
  • Updated the following figures:
    • Nios V/m Processor IP instance in Platform Designer
    • Example connection of Nios V processor with other peripherals in Platform Designer
    • hal.linker Settings for QSPI Flash
    • Connections for Nios V Processor Project
    • hal.linker Settings
    • Linker Region Settings
    • hal.make Settings
    • BSP Driver tab
  • Added Enable Reset from Debug Module to the following figures:
    • Parameter Editor Settings
    • Nios V Parameter Editor Settings
  • Removed the mention of exception vector, exception RAM, exception agent, and .exception in the following topics:
    • Defining System Component Design
    • Nios V Processor Design, Configuration and Boot Flow (Control Block-based Device)
    • Reset Agent Settings for Nios V Processor Execute-In-Place Method
    • Reset Agent Settings for Nios V Processor Boot-copier Method
    • Nios V Processor Design, Configuration and Boot Flow (SDM-based Devices)
    • Nios V Processor Application Copied from Configuration QSPI Flash to RAM Using Boot Copier (SDM Bootloader)
    • Table: Description of Memory Organization
    • Design, Configuration and Booting Flow in Nios V Processor Application Executes in-place from OCRAM
    • Table: Summary of Nios V Processor Vector Configurations and BSP Settings
  • Edited Configuring BSP Editor and Generating the BSP Project in Nios V Processor Design, Configuration and Boot Flow (Control Block-based Device).
  • Added Table: Settings for BSP Editor in Software Design Flow (SDM Bootloader Project).
2022.08.12 22.2 21.3.0
  • Edited the steps in Programming Nios V/m into the FPGA Device.
  • Edited Table: Debug Tab Parameter to add the description for dbg_reset.
  • Edited topic On-Chip Memory Configuration - RAM or ROM topic. Added a link to Nios V Processor Application Execute-In-Place from OCRAM.
  • Changed the topic title from Clocks and Resets to Clocks and Resets Best Practices.
  • Added the following new topics:
    • Reset Request Interface
    • Typical Use Cases
    • Assigning a Default Agent
  • Added a note about configuring the RISC-V toolchain prefix in the topic Eclipse CDT for Embedded C/C++ Developer.
2022.06.21 22.2 21.3.0
  • Added the support for RiscFree IDE for Intel® FPGAs.
  • Removed the following topics:
    • Setting Up Open-Source Tools
    • Building the Application Project using Eclipse Embedded CDT
    • Building the Application Project using the Command-Line Interface
    • Creating a Software Project using Platform Designer & Eclipse Embedded CDT
    • Creating a Software Project Using Command Line
  • Edited the Figure : Software Design Flow to include RiscFree IDE for Intel® FPGAs
  • Added the following topics:
    • Nios V Software Development Flow
    • Board Support Package Project
    • Application Project
    • Intel FPGA Embedded Development Tools
    • Nios V Board Support Package Editor
    • RiscFree* IDE for Intel FPGA
    • Eclipse* CDT for Embedded C/C++ Developer
    • Nios V Utilities Tools
    • File Format Conversion Tools
    • Other Utilities Tools
    • Generating the Board Support Package
    • Generating the Application Project File
    • Building the Application Project
2022.04.04 22.1 21.2.0 Initial release.
Level Two Title