Nios® V Embedded Processor Design Handbook

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ID 726952
Date 8/12/2022
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Document Table of Contents
Document Table of Contents x
1. About This Document 2. About the Nios® V Embedded Processor 3. Nios® V Processor Hardware System Design with Intel® Quartus® Prime Pro Edition and Platform Designer 4. Nios® V Processor Software System Design 5. Nios® V Processor Configuration and Booting Solutions 6. Nios® V Processor - Using the MicroC/TCP-IP Stack 7. Nios® V Processor Debugging, Verifying, and Simulating 8. Nios® V Embedded Processor Design Handbook Archives 9. Document Revision History for the Nios® V Embedded Processor Design Handbook
2. About the Nios® V Embedded Processor x
2.1. Intel® FPGA IP and Soft-Core Processors Overview 2.2. Embedded System Design 2.3. Nios® V Processor Quick Start Guide
2.3. Nios® V Processor Quick Start Guide x
2.3.1. System Requirements 2.3.2. Nios® V/m Processor Example Design 2.3.3. Software Design Flow 2.3.4. Programming Nios® V/m into the FPGA Device
2.3.1. System Requirements x
2.3.1.1. Hardware and Software Requirements
2.3.2. Nios® V/m Processor Example Design x
2.3.2.1. Generating the Example Design Through Graphical User Interface 2.3.2.2. Generating the Nios® V/m Processor Example Design Using the Command-Line Interface
2.3.2.1. Generating the Example Design Through Graphical User Interface x
2.3.2.1.1. Generating the Nios® V/m Processor Example Design in Platform Designer 2.3.2.1.2. Generating the Nios® V/m Processor Example Design System in Platform Designer
2.3.3. Software Design Flow x
2.3.3.1. Generating the Board Support Package 2.3.3.2. Generating the Application Project File 2.3.3.3. Building the Application Project
2.3.3.1. Generating the Board Support Package x
2.3.3.1.1. Generating the Board Support Package using the BSP Editor GUI 2.3.3.1.2. Generating the Board Support Package using the Command-Line Interface
3. Nios® V Processor Hardware System Design with Intel® Quartus® Prime Pro Edition and Platform Designer x
3.1. Creating Nios® V Processor System Design with Platform Designer 3.2. Integrating Platform Designer System into the Intel® Quartus® Prime Project 3.3. Designing a Nios® V Processor Memory System 3.4. Clocks and Resets Best Practices 3.5. Assigning a Default Agent
3.1. Creating Nios® V Processor System Design with Platform Designer x
3.1.1. Instantiating Nios® V/m Processor IP Core 3.1.2. Defining System Component Design 3.1.3. Specifying Base Addresses and Interrupt Request Priorities
3.1.1. Instantiating Nios® V/m Processor IP Core x
3.1.1.1. Configure Nios® V Processor Parameters 3.1.1.2. Generate Nios® V processor example design from Platform Designer
3.1.1.1. Configure Nios® V Processor Parameters x
3.1.1.1.1. Debug Tab 3.1.1.1.2. Vectors Tab
3.2. Integrating Platform Designer System into the Intel® Quartus® Prime Project x
3.2.1. Instantiating the Nios® V Processor System Module in the Intel® Quartus® Prime Project 3.2.2. Connecting Signals and Assigning Physical Pin Locations 3.2.3. Constraining the Intel FPGA Design
3.3. Designing a Nios® V Processor Memory System x
3.3.1. Volatile Memory 3.3.2. Non-Volatile Memory 3.3.3. On-Chip Memory Configuration – RAM or ROM
3.4. Clocks and Resets Best Practices x
3.4.1. Reset Request Interface
3.4.1. Reset Request Interface x
3.4.1.1. Typical Use Cases
4. Nios® V Processor Software System Design x
4.1. Nios V Processor Software Development Flow 4.2. Intel FPGA Embedded Development Tools
4.1. Nios V Processor Software Development Flow x
4.1.1. Board Support Package Project 4.1.2. Application Project
4.2. Intel FPGA Embedded Development Tools x
4.2.1. Nios V Board Support Package Editor 4.2.2. RiscFree* IDE for Intel FPGAs 4.2.3. Eclipse CDT for Embedded C/C++ Developer 4.2.4. Nios V Utilities Tools 4.2.5. File Format Conversion Tools 4.2.6. Other Utilities Tools
5. Nios® V Processor Configuration and Booting Solutions x
5.1. Introduction 5.2. Linking Applications 5.3. Nios® V Processor Booting Methods 5.4. Introduction to Nios® V Processor Booting Methods 5.5. Nios® V Processor Booting from Configuration QSPI Flash 5.6. Nios V Processor Booting from On-Chip Memory (OCRAM) 5.7. Summary of Nios V Processor Vector Configuration and BSP Settings
5.2. Linking Applications x
5.2.1. Linking Behaviour
5.2.1. Linking Behaviour x
5.2.1.1. Default BSP Linking 5.2.1.2. Configurable BSP Linking
5.4. Introduction to Nios® V Processor Booting Methods x
5.4.1. Nios® V Processor Application Execute-In-Place from Boot Flash 5.4.2. Nios® V Processor Application Copied from Boot Flash to RAM Using Boot Copier 5.4.3. Nios® V Processor Application Execute-In-Place from OCRAM
5.4.1. Nios® V Processor Application Execute-In-Place from Boot Flash x
5.4.1.1. alt_load()
5.4.2. Nios® V Processor Application Copied from Boot Flash to RAM Using Boot Copier x
5.4.2.1. GSFI Bootloader 5.4.2.2. SDM Bootloader
5.5. Nios® V Processor Booting from Configuration QSPI Flash x
5.5.1. Nios V Processor Design, Configuration and Boot Flow (Control Block-based Device) 5.5.2. Nios V Processor Design, Configuration and Boot Flow (SDM-based Devices)
5.5.1. Nios V Processor Design, Configuration and Boot Flow (Control Block-based Device) x
5.5.1.1. Nios® V Processor Application Executes-In-Place from Configuration QSPI Flash 5.5.1.2. Nios® V Processor Application Copied from Configuration QSPI Flash to RAM Using Boot Copier (GSFI Bootloader) 5.5.1.3. GSFI Bootloader Example Design
5.5.1.1. Nios® V Processor Application Executes-In-Place from Configuration QSPI Flash x
5.5.1.1.1. Hardware Design Flow 5.5.1.1.2. Software Design Flow Creating the BSP Project Application Configuring BSP Editor and Generating the BSP Project Generating the Application Project File Building the Application Project Generating HEX File 5.5.1.1.3. Programming Files Generation 5.5.1.1.4. QSPI Flash Programming
5.5.1.2. Nios® V Processor Application Copied from Configuration QSPI Flash to RAM Using Boot Copier (GSFI Bootloader) x
5.5.1.2.1. Hardware Design Flow 5.5.1.2.2. Software Design Flow 5.5.1.2.3. Programming Files Generation 5.5.1.2.4. QSPI Flash Programming
5.5.2. Nios V Processor Design, Configuration and Boot Flow (SDM-based Devices) x
5.5.2.1. Nios V Processor Application Copied from Configuration QSPI Flash to RAM Using Boot Copier (SDM Bootloader) 5.5.2.2. SDM Bootloader Example Design
5.5.2.1. Nios V Processor Application Copied from Configuration QSPI Flash to RAM Using Boot Copier (SDM Bootloader) x
5.5.2.1.1. Hardware Design Flow 5.5.2.1.2. Software Design Flow 5.5.2.1.3. Software Design Flow (SDM Bootloader Project) 5.5.2.1.4. Software Design Flow (User Application Project) 5.5.2.1.5. Programming Files Generation 5.5.2.1.6. QSPI Flash Programming SDM
5.6. Nios V Processor Booting from On-Chip Memory (OCRAM) x
5.6.1. Nios V Processor Application Executes in-place from OCRAM
5.6.1. Nios V Processor Application Executes in-place from OCRAM x
5.6.1.1. Hardware Design Flow 5.6.1.2. Software Design Flow 5.6.1.3. Programming
6. Nios® V Processor - Using the MicroC/TCP-IP Stack x
6.1. Introduction 6.2. Software Architecture 6.3. Support and Licensing 6.4. MicroC/TCP-IP Example Designs 6.5. Development Flow 6.6. Operating the Example Designs 6.7. Optional Configuration 6.8. MicroC/TCP-IP Simple Socket Server Concepts
6.4. MicroC/TCP-IP Example Designs x
6.4.1. Hardware and Software Requirements 6.4.2. Overview 6.4.3. Acquiring the Example Design Files 6.4.4. Hardware Design Files 6.4.5. Software Design Files
6.4.5. Software Design Files x
6.4.5.1. MicroC/TCP-IP IPerf Example Design 6.4.5.2. MicroC/TCP-IP Simple Socket Server Example Design
6.5. Development Flow x
6.5.1. Hardware Development Flow 6.5.2. Software Development Flow 6.5.3. Device Programming
6.5.2. Software Development Flow x
6.5.2.1. Creating a BSP project 6.5.2.2. Configuring the BSP 6.5.2.3. Creating an Application Project 6.5.2.4. Building the Application Project 6.5.2.5. HEX File Generation
6.6. Operating the Example Designs x
6.6.1. Operating the MicroC/TCP-IP IPerf 6.6.2. Operating the MicroC/TCP-IP Simple Socket Server
6.7. Optional Configuration x
6.7.1. Configuring Hardware Name 6.7.2. Configuring MAC and IP Addresses 6.7.3. Configuring MicroC/TCP-IP Initialization 6.7.4. Configuring iPerf Server Auto-Initialization
6.7.3. Configuring MicroC/TCP-IP Initialization x
6.7.3.1. Network Task Configuration 6.7.3.2. Network Interface Configuration
6.8. MicroC/TCP-IP Simple Socket Server Concepts x
6.8.1. MicroC/OS-II Resources 6.8.2. Error Handling 6.8.3. MicroC/TCP-IP Stack Default Configuration
7. Nios® V Processor Debugging, Verifying, and Simulating x
7.1. Debugging Nios® V Processor Software Designs 7.2. Debugging Tools 7.3. Additional Embedded Design Considerations 7.4. Simulating Nios® V Processor Designs
7.1. Debugging Nios® V Processor Software Designs x
7.1.1. OpenOCD and Eclipse Embedded CDT 7.1.2. Objdump File 7.1.3. Show Make Commands
7.3. Additional Embedded Design Considerations x
7.3.1. JTAG Signal Integrity 7.3.2. Additional Memory Space for System Prototyping
7.4. Simulating Nios® V Processor Designs x
7.4.1. Prerequisites 7.4.2. Setting Up and Generating Your Simulation Environment in Platform Designer 7.4.3. Creating Nios V Processor Software 7.4.4. Generating Memory Initialization File 7.4.5. Generating System Simulation Files 7.4.6. Running Simulation in the QuestaSim Simulator Using Command Line
7.4.2. Setting Up and Generating Your Simulation Environment in Platform Designer x
7.4.2.1. Using IP and Platform Designer Simulation Setup Scripts
7.4.3. Creating Nios V Processor Software x
7.4.3.1. Generating the Board Support Package 7.4.3.2. Generating the Application Project File 7.4.3.3. Building the Application Project
1. About This Document
2. About the Nios® V Embedded Processor
3. Nios® V Processor Hardware System Design with Intel® Quartus® Prime Pro Edition and Platform Designer
4. Nios® V Processor Software System Design
5. Nios® V Processor Configuration and Booting Solutions
6. Nios® V Processor - Using the MicroC/TCP-IP Stack
7. Nios® V Processor Debugging, Verifying, and Simulating
8. Nios® V Embedded Processor Design Handbook Archives
9. Document Revision History for the Nios® V Embedded Processor Design Handbook

5.5.1.1.2. Software Design Flow

This section provides the design flow to generate and build a Nios® V processor software project. To ensure a streamlined build flow, you are encouraged to create a similar directory tree in your design project. The software design flow is based on this directory tree.

Use the following steps to create the software project directory tree:

  1. In your design project folder, create a folder called software.
  2. In the software folder, create two folders called app and bsp.
    Figure 24. Software Project Directory Tree

Creating the BSP Project Application

You must edit the BSP editor settings according to the selected Nios® V processor boot options and the exception agent.

To launch the BSP Editor, perform the following steps:

  1. In the Platform Designer window, select File > New BSP. The Create New BSP windows appears.
  2. For BSP setting file, navigate to the software/bsp folder and name the BSP as settings.bsp.

BSP path: <project directory>/software/bsp/settings.bsp

  1. For System file (qsys or sopcinfo), select the Nios V/m processor Platform Designer system (*.qsys).
  2. For Quartus project, select the Quartus Project File.
  3. For Revision, select the correct revision.
  4. For CPU name, select the Nios V/m processor.
  5. Select the Operating system as Altera HAL.
  6. Click Create to create the BSP file.
Figure 25. Create New BSP window

Configuring BSP Editor and Generating the BSP Project

  1. Go to Main > Settings > Advanced > hal.linker.
  2. If exception agent is set to OCRAM or External RAM, enable the following:
    • allow_code_at_reset
    • enable_alt_load
    • enable_alt_load_copy_rodata
    • enable_alt_load_copy_rwdata
    • enable_alt_load_copy_exceptions
    Figure 26. hal.linker Settings for Exception Agent OCRAM or External RAM
  3. If exception agent is set to QSPI flash, enable the following:
    • allow_code_at_reset
    • enable_alt_load
    • enable_alt_load_copy_rodata
    • enable_alt_load_copy_rwdata
    Figure 27. hal.linker Settings for QSPI Flash
  4. In the BSP Editor, click BSP Linker Script.
  5. Set the .text item in the Linker Section Name to the QSPI flash in the Linker Region Name.
  6. Set the rest of the items in the Linker Section Name list to the OCRAM or external RAM.
    Figure 28. Linker Region Settings
  7. Click Generate BSP. Make sure the BSP generation is successful.
  8. Close the BSP Editor.

Generating the Application Project File

  1. Navigate to the software/app folder and create your Nios® V application source code.
  2. Launch the Nios V Command Shell.
  3. Execute the command below to generate the application CMakeLists.txt. 
niosv-app --app-dir=software/app --bsp-dir=software/bsp \
  --srcs=software/app/<Nios V application source code>

Building the Application Project

You can choose to build the application project using the RiscFree* IDE for Intel FPGAs, Eclipse Embedded CDT or through the command line interface (CLI).

If you prefer using CLI, you can build the application using the following command:

cmake -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=Debug -B \
  software/app/debug -S software/app 
 make -C software/app/debug

The application (.elf) file is created in software/app/debug folder.

Generating HEX File

You must generate a .hex file from your application .elf file, so you can create a .jic file suitable for programming flash devices.

  1. Launch the Nios V Command Shell.
  2. For Nios® V processor application execute-in-place (XIP) from configuration QSPI flash, use the following commands line to convert the ELF to HEX for your application. The commands create the application (.hex) file. 
elf2flash --input software/app/debug/<Nios V application>.elf \
  --output flash.srec --reset <reset offset + base address of GSFI AVL MEM> \
  --base <base address of GSFI AVL MEM> \
  --end <end address of GSFI AVL MEM>
riscv32-unknown-elf-objcopy --input-target srec --output-target ihex \
  flash.srec <Nios V application>.hex
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