Nios® V Embedded Processor Design Handbook

ID 726952
Date 8/12/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

3.3.3. On-Chip Memory Configuration – RAM or ROM

You can configure Intel FPGA On-Chip Memory IPs as RAM or ROM.
  • RAM provides read and write capability and has a volatile nature. If you are booting the Nios® V processor from an On-Chip RAM, you must make sure boot content is preserved and not corrupted in the event of a reset during run time.
  • If a Nios® V processor is booting from ROM, any software bug on the Nios® V processor cannot erroneously overwrite the contents of On-Chip Memory. Thus, reducing the risk of boot software corruption.