Nios® V Embedded Processor Design Handbook

ID 726952
Date 8/12/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

5.3. Nios® V Processor Booting Methods

There are a few methods to boot up the Nios® V processor in Intel FPGA devices. The methods to boot up Nios® V processor vary according to the flash memory selection and device families.

Table 10.  Supported Flash Memories with Respective Boot Options
Supported Boot Memories Device Nios V Booting Methods Application Runtime Location Boot Copier
Configuration QSPI Flash (for Active Serial configuration) Control block-based devices 2 (with Generic Serial Flash Interface Intel FPGA IP)

Nios V processor application execute-in-place from configuration QSPI flash

Configuration QSPI flash (XIP) + OCRAM/ External RAM (for writable data sections) alt_load() function
Nios V processor application copied from configuration QSPI flash to RAM using boot copier OCRAM/ External RAM GSFI bootloader
SDM-based devices 3 (with Mailbox Client Intel FPGA IP) Nios V processor application copied from configuration QSPI flash to RAM using boot copier OCRAM/ External RAM SDM bootloader

On-chip Memory (OCRAM)

All supported Intel FPGA devices 4 Nios V processor application execute-in-place from OCRAM OCRAM alt_load() function
Figure 14. Nios V Processor Boot Flow
2 Control block-based devices refer to the Intel® Cyclone® 10 GX and Intel® Arria® 10 devices.
3 SDM-based devices refer to the Intel® Stratix® 10 and Intel® Agilex™ devices.
4 The supported Intel FPGA devices refer to the Intel® Cyclone® 10 GX, Intel Arria 10, Intel® Stratix® 10 and Intel® Agilex™ devices.