F-Tile Dynamic Reconfiguration Design Example User Guide

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ID 710582
Date 9/26/2022
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Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Detailed Description for CPRI Multirate Design Example 3. Detailed Description for Ethernet Multirate Design Example 4. Detailed Description for PMA/FEC Direct PHY Multirate Design Example 5. Detailed Description for Ethernet to CPRI Design Example 6. F-Tile Dynamic Reconfiguration Design Example User Guide Archives 7. Document Revision History for F-Tile Dynamic Reconfiguration Design Example User Guide
1. Quick Start Guide x
1.1. Hardware and Software Requirements 1.2. Generating the Design 1.3. Directory Structure 1.4. Compiling the Compilation-Only Project 1.5. Simulating the Design Example Testbench 1.6. Compiling and Configuring the Design Example in Hardware 1.7. Testing the Hardware Design Example
1.2. Generating the Design x
1.2.1. CPRI Multirate Design Example Parameters 1.2.2. Ethernet Multirate Design Example Parameters 1.2.3. PMA/FEC Direct PHY Multirate Design Example Parameters 1.2.4. Ethernet to CPRI Design Example Parameters
2. Detailed Description for CPRI Multirate Design Example x
2.1. CPRI Multirate Design Example: Functional Description 2.2. CPRI Multirate Design Example: Registers
2.1. CPRI Multirate Design Example: Functional Description x
2.1.1. CPRI Multirate Design Example: Simulation Testbench 2.1.2. CPRI Multirate Hardware Design Example 2.1.3. CPRI Multirate Design Example: Reset Scheme
3. Detailed Description for Ethernet Multirate Design Example x
3.1. Ethernet Multirate Design Example: Functional Description 3.2. Ethernet Multirate Design Example: Registers
3.1. Ethernet Multirate Design Example: Functional Description x
3.1.1. Ethernet Multirate Design Example: Simulation Testbench 3.1.2. Ethernet Multirate Hardware Design Example
4. Detailed Description for PMA/FEC Direct PHY Multirate Design Example x
4.1. PMA/FEC Direct PHY Multirate Design Example: Functional Description 4.2. PMA/FEC Direct PHY Multirate Design Example: Registers
4.1. PMA/FEC Direct PHY Multirate Design Example: Functional Description x
4.1.1. PMA/FEC Direct PHY Multirate Design Example: Simulation Testbench 4.1.2. PMA/FEC Direct PHY Multirate Hardware Design Example
5. Detailed Description for Ethernet to CPRI Design Example x
5.1. Ethernet to CPRI Design Example: Functional Description
5.1. Ethernet to CPRI Design Example: Functional Description x
5.1.1. Ethernet to CPRI Dynamic Reconfiguration Design Example: Simulation Testbench
1. Quick Start Guide
2. Detailed Description for CPRI Multirate Design Example
3. Detailed Description for Ethernet Multirate Design Example
4. Detailed Description for PMA/FEC Direct PHY Multirate Design Example
5. Detailed Description for Ethernet to CPRI Design Example
6. F-Tile Dynamic Reconfiguration Design Example User Guide Archives
7. Document Revision History for F-Tile Dynamic Reconfiguration Design Example User Guide

1.2. Generating the Design

Figure 2. Procedure
Follow these steps to generate a design example:
  1. In the IP Catalog, locate and select F-Tile Dynamic Reconfiguration Suite Intel FPGA IP. The New IP Variation window appears.
  2. Specify a top-level name <your_ip> for your custom IP variation. The parameter editor saves the IP variation settings in a file named as <your_ip>.ip.
  3. On the IP tab, specify the parameters for your IP core variation.
  4. On the Example Design tab, under Available Example Design, select the Protocol and Base Variant.
  5. On the Example Design tab, under Example Design Files, select the Simulation option to generate the testbench and the compilation-only project. Select the Synthesis option to generate the hardware design example. You must select at least one of the Simulation and Synthesis options to generate the design example.
  6. On the Example Design tab, under Generated HDL Format, select Verilog HDL.
  7. On the Example Design tab, under Target Development Kit, select the Board.
    • If NONE is selected, the device OPN of the generated example design is your device selection while creating the Intel® Quartus® Prime project.
    • If Agilex I-Series Transceiver-SoC Development Kit is selected, the device OPN of the generated example design is AGIB027R31B1E2VR0 (device OPN of the development kit). The VID settings is generated in the qsf file of the hardware design example.
  8. Click the Generate Example Design button. The Select Example Design Directory window appears.

    If you want to modify the design example directory path or name from the default value (dr_f_0_example_design), browse to the new path and type the new design example directory name (<design_example_dir>).


Section Content
CPRI Multirate Design Example Parameters
Ethernet Multirate Design Example Parameters
PMA/FEC Direct PHY Multirate Design Example Parameters
Ethernet to CPRI Design Example Parameters

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