F-Tile Dynamic Reconfiguration Design Example User Guide

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ID 710582
Date 9/26/2022
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Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Detailed Description for CPRI Multirate Design Example 3. Detailed Description for Ethernet Multirate Design Example 4. Detailed Description for PMA/FEC Direct PHY Multirate Design Example 5. Detailed Description for Ethernet to CPRI Design Example 6. F-Tile Dynamic Reconfiguration Design Example User Guide Archives 7. Document Revision History for F-Tile Dynamic Reconfiguration Design Example User Guide
1. Quick Start Guide x
1.1. Hardware and Software Requirements 1.2. Generating the Design 1.3. Directory Structure 1.4. Compiling the Compilation-Only Project 1.5. Simulating the Design Example Testbench 1.6. Compiling and Configuring the Design Example in Hardware 1.7. Testing the Hardware Design Example
1.2. Generating the Design x
1.2.1. CPRI Multirate Design Example Parameters 1.2.2. Ethernet Multirate Design Example Parameters 1.2.3. PMA/FEC Direct PHY Multirate Design Example Parameters 1.2.4. Ethernet to CPRI Design Example Parameters
2. Detailed Description for CPRI Multirate Design Example x
2.1. CPRI Multirate Design Example: Functional Description 2.2. CPRI Multirate Design Example: Registers
2.1. CPRI Multirate Design Example: Functional Description x
2.1.1. CPRI Multirate Design Example: Simulation Testbench 2.1.2. CPRI Multirate Hardware Design Example 2.1.3. CPRI Multirate Design Example: Reset Scheme
3. Detailed Description for Ethernet Multirate Design Example x
3.1. Ethernet Multirate Design Example: Functional Description 3.2. Ethernet Multirate Design Example: Registers
3.1. Ethernet Multirate Design Example: Functional Description x
3.1.1. Ethernet Multirate Design Example: Simulation Testbench 3.1.2. Ethernet Multirate Hardware Design Example
4. Detailed Description for PMA/FEC Direct PHY Multirate Design Example x
4.1. PMA/FEC Direct PHY Multirate Design Example: Functional Description 4.2. PMA/FEC Direct PHY Multirate Design Example: Registers
4.1. PMA/FEC Direct PHY Multirate Design Example: Functional Description x
4.1.1. PMA/FEC Direct PHY Multirate Design Example: Simulation Testbench 4.1.2. PMA/FEC Direct PHY Multirate Hardware Design Example
5. Detailed Description for Ethernet to CPRI Design Example x
5.1. Ethernet to CPRI Design Example: Functional Description
5.1. Ethernet to CPRI Design Example: Functional Description x
5.1.1. Ethernet to CPRI Dynamic Reconfiguration Design Example: Simulation Testbench
1. Quick Start Guide
2. Detailed Description for CPRI Multirate Design Example
3. Detailed Description for Ethernet Multirate Design Example
4. Detailed Description for PMA/FEC Direct PHY Multirate Design Example
5. Detailed Description for Ethernet to CPRI Design Example
6. F-Tile Dynamic Reconfiguration Design Example User Guide Archives
7. Document Revision History for F-Tile Dynamic Reconfiguration Design Example User Guide

4.1.2. PMA/FEC Direct PHY Multirate Hardware Design Example

Figure 24. PMA/FEC Direct PHY Multirate Hardware Design Example Block Diagram: 50G-1 Base Variant

In the hardware design example, the ISSP modules control the DUT IP reset signals, dr_mode selection and shows the status signals. The hardware test scripts open service to the ISSP to read and drive the values. A JTAG host is instantiated to access the Avalon® memory-mapped interface.

The hardware design example executes the dynamic reconfiguration transition process based on user selection as stated in src/parameter.tcl file and checks the DUT IP status. There is a default dynamic reconfiguration transition sequence, but user can always modify the DR_TRANSITION array variable in src/parameter.tcl file.

DR_TRANSITION: Intended DR sequence array, size of this array variable determines the number of dynamic reconfiguration to be performed. For example, if you want to achieve the following dynamic reconfiguration sequence: 1x50G > 1x25G > 1x50G KPFEC > 1x24.33024G > 1x50G, the variables changes are: 
set DR_TRANSITION(0) "1x25G"
set DR_TRANSITION(1) "1x50G KPFEC"
set DR_TRANSITION(2) "1x24.33024G"
set DR_TRANSITION(3) "1x50G

Hardware Flow for Design Example:

The hardware test design <design_example_dir>/hardware_test_design/ directory contains a hwtest subdirectory that contains .tcl script for dynamic reconfiguration hardware testing. Follow the steps shown below to test the design example in hardware.
Figure 25. Hardware Flow for PMA/FEC Direct PHY Multirate Hardware Design Example
  1. In the Intel® Quartus® Prime Pro Edition software, open the Intel® Quartus® Prime project: <design_example_dir>/hardware_test_design/dphy_f_hw.qpf.
  2. Click Processing > Start Compilation to compile the design and generate the .sof.
  3. Download the .sof into your Intel Agilex device.
  4. Configure the board clocks as required.
    Note: This step is not required if the Agilex I-Series Transceiver-SoC Development Kit is selected.
  5. Open System Console in Intel® Quartus® Prime Pro Edition software by clicking Tools > System Debugging Tools > System Console.
  6. Navigate to the hwtest directory.
    cd hwtest
  7. Run the script. The script performs the dynamic reconfiguration steps.
    source main_script.tcl
  8. Analyze the results. A successful run displays Test <ftile_dphy_dr_test> Passed in the System Console window.

The sample output for the PMA/FEC Direct PHY Multirate hardware design example is shown below.

Sample output for PMA/FEC Direct PHY Multirate hardware design example: 
% cd hwtest

$source main_script.tcl
Info: Number of Channels = 1
Info: JTAG Port ID       = 2
Info: Power Up Variant   = 1x50G
INFO: Start of ftile_dphy_dr_test

INFO: Basic DPHY DR test

	INFO: Set Reconfig Reset
	INFO: write_value is 0x1
	INFO: Release Reconfig Reset
	INFO: write_value is 0x0
	INFO: Set DR mode...
	INFO: DR mode is 0x0

...........

*******
*******

	INFO: Channel 0: Set TX Reset
	INFO: write_value is 0x4
	INFO: Channel 0: Set RX Reset
	INFO: write_value is 0x6
	INFO: get_reset_ack_status  -----
	INFO: Channel 0 : Checking tx reset ack status...
		INFO: tx_reset_ack_status_0 = 0x3
	INFO: TX fully in reset state 
	INFO: Channel 0 : Checking rx reset ack status...
		INFO: rx_reset_ack_status_0 = 0x3
	INFO: RX fully in reset state 
	INFO: Start DR selection-----
		INFO: DR transition is 1x50G -----
	INFO: Channel: 0 Configuring ED to PMA_DIR 1x50G ....
	INFO: Wait for DR Ready....
	INFO: configuring DR Profile 1x50G....
	INFO: Trigger DR interrupt
	INFO: Wait for DR interrupt Ack....
	INFO: DR Request acknowledged
	INFO: Wait for DR Config to be done....
	INFO: DONE Reconfigure to 1x50G.
	INFO: Set DR mode...
	INFO: DR mode is 0x0
	INFO: Channel 0: Release TX Reset
	INFO: write_value is 0x2
	INFO: Channel 0: Release RX Reset
	INFO: write_value is 0x0
	INFO: Channel 0 : Run test...
	INFO: Read out probe data: 0x7dc
	INFO: Data locked with no error

*******
*******


Info: End of ftile_dphy_dr_test 

Info: Test <ftile_dphy_dr_test> Passed
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