F-Tile Dynamic Reconfiguration Design Example User Guide

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ID 710582
Date 9/26/2022
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Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Detailed Description for CPRI Multirate Design Example 3. Detailed Description for Ethernet Multirate Design Example 4. Detailed Description for PMA/FEC Direct PHY Multirate Design Example 5. Detailed Description for Ethernet to CPRI Design Example 6. F-Tile Dynamic Reconfiguration Design Example User Guide Archives 7. Document Revision History for F-Tile Dynamic Reconfiguration Design Example User Guide
1. Quick Start Guide x
1.1. Hardware and Software Requirements 1.2. Generating the Design 1.3. Directory Structure 1.4. Compiling the Compilation-Only Project 1.5. Simulating the Design Example Testbench 1.6. Compiling and Configuring the Design Example in Hardware 1.7. Testing the Hardware Design Example
1.2. Generating the Design x
1.2.1. CPRI Multirate Design Example Parameters 1.2.2. Ethernet Multirate Design Example Parameters 1.2.3. PMA/FEC Direct PHY Multirate Design Example Parameters 1.2.4. Ethernet to CPRI Design Example Parameters
2. Detailed Description for CPRI Multirate Design Example x
2.1. CPRI Multirate Design Example: Functional Description 2.2. CPRI Multirate Design Example: Registers
2.1. CPRI Multirate Design Example: Functional Description x
2.1.1. CPRI Multirate Design Example: Simulation Testbench 2.1.2. CPRI Multirate Hardware Design Example 2.1.3. CPRI Multirate Design Example: Reset Scheme
3. Detailed Description for Ethernet Multirate Design Example x
3.1. Ethernet Multirate Design Example: Functional Description 3.2. Ethernet Multirate Design Example: Registers
3.1. Ethernet Multirate Design Example: Functional Description x
3.1.1. Ethernet Multirate Design Example: Simulation Testbench 3.1.2. Ethernet Multirate Hardware Design Example
4. Detailed Description for PMA/FEC Direct PHY Multirate Design Example x
4.1. PMA/FEC Direct PHY Multirate Design Example: Functional Description 4.2. PMA/FEC Direct PHY Multirate Design Example: Registers
4.1. PMA/FEC Direct PHY Multirate Design Example: Functional Description x
4.1.1. PMA/FEC Direct PHY Multirate Design Example: Simulation Testbench 4.1.2. PMA/FEC Direct PHY Multirate Hardware Design Example
5. Detailed Description for Ethernet to CPRI Design Example x
5.1. Ethernet to CPRI Design Example: Functional Description
5.1. Ethernet to CPRI Design Example: Functional Description x
5.1.1. Ethernet to CPRI Dynamic Reconfiguration Design Example: Simulation Testbench
1. Quick Start Guide
2. Detailed Description for CPRI Multirate Design Example
3. Detailed Description for Ethernet Multirate Design Example
4. Detailed Description for PMA/FEC Direct PHY Multirate Design Example
5. Detailed Description for Ethernet to CPRI Design Example
6. F-Tile Dynamic Reconfiguration Design Example User Guide Archives
7. Document Revision History for F-Tile Dynamic Reconfiguration Design Example User Guide

2.1.1. CPRI Multirate Design Example: Simulation Testbench

Figure 7. Simulation Testbench Block Diagram

The testbench program is controlling the testbench components via Avalon® memory-mapped interface access, status and control signals. The Avalon® memory-mapped interface arbiter is used to decode the Avalon® memory-mapped interface access from testbench program into multiple Avalon® memory-mapped interface slaves.

Simulation Flow for Design Example:
  1. Disable the Testbench packet round-trip measurement.
  2. Power up the CPRI PHY Multirate IP DUT based on profile 0 (24G RS-FEC).
  3. Initialize the testbench variables based on power-up profile. The variables are:
    • cpri_speed: To indicate the speed of the current profile.
    • enable_rsfec: To indicate whether RS-FEC is enabled or disabled for the current profile.
    • current_dr_profile: To indicate the ID of the current profile.
  4. Perform dynamic reconfiguration.
  5. Check the testbench error flag and determine whether testbench passed or failed. This error flag is set to 1 if there is any error after dynamic reconfiguration traffic tests.
For customization, you can modify the DR_NUM and DR_SEQ localparam to configure test flow. Profile ID is passed into Dynamic Reconfiguration IP to configure the intended dynamic reconfiguration task.
  • DR_NUM: Number of Dynamic Reconfiguration transition
  • DR_SEQ: Dynamic Reconfiguration sequence
For example, you want to achieve this Dynamic Reconfiguration sequence: 24G RS-FEC > 10G > 4.9G. The localparams changes are:
  • DR_NUM = 2
  • DR_SEQ = {DR_TO_4P9G, DR_TO_10G};
Default configuration for the design example: 
localparam DR_TO_24G_RSFEC   = 4'h0;
localparam DR_TO_24G         = 4'h1;
localparam DR_TO_12G_RSFEC   = 4'h2;
localparam DR_TO_12G         = 4'h3;
localparam DR_TO_10G_RSFEC   = 4'h4;
localparam DR_TO_10G         = 4'h5;
localparam DR_TO_9P8G        = 4'h6;
localparam DR_TO_6G          = 4'h7;
localparam DR_TO_4P9G        = 4'h8;
localparam DR_TO_3G          = 4'h9;
localparam DR_TO_2P4G        = 4'ha;
localparam DR_TO_1G          = 4'hb;

localparam DR_NUM = 5;
localparam [3:0] DR_SEQ [DR_NUM-1 : 0] = {DR_TO_24G_RSFEC, DR_TO_2P4G, DR_TO_4P9G, DR_TO_9P8G, DR_TO_10G};
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