F-Tile Dynamic Reconfiguration Design Example User Guide

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ID 710582
Date 9/26/2022
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Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Detailed Description for CPRI Multirate Design Example 3. Detailed Description for Ethernet Multirate Design Example 4. Detailed Description for PMA/FEC Direct PHY Multirate Design Example 5. Detailed Description for Ethernet to CPRI Design Example 6. F-Tile Dynamic Reconfiguration Design Example User Guide Archives 7. Document Revision History for F-Tile Dynamic Reconfiguration Design Example User Guide
1. Quick Start Guide x
1.1. Hardware and Software Requirements 1.2. Generating the Design 1.3. Directory Structure 1.4. Compiling the Compilation-Only Project 1.5. Simulating the Design Example Testbench 1.6. Compiling and Configuring the Design Example in Hardware 1.7. Testing the Hardware Design Example
1.2. Generating the Design x
1.2.1. CPRI Multirate Design Example Parameters 1.2.2. Ethernet Multirate Design Example Parameters 1.2.3. PMA/FEC Direct PHY Multirate Design Example Parameters 1.2.4. Ethernet to CPRI Design Example Parameters
2. Detailed Description for CPRI Multirate Design Example x
2.1. CPRI Multirate Design Example: Functional Description 2.2. CPRI Multirate Design Example: Registers
2.1. CPRI Multirate Design Example: Functional Description x
2.1.1. CPRI Multirate Design Example: Simulation Testbench 2.1.2. CPRI Multirate Hardware Design Example 2.1.3. CPRI Multirate Design Example: Reset Scheme
3. Detailed Description for Ethernet Multirate Design Example x
3.1. Ethernet Multirate Design Example: Functional Description 3.2. Ethernet Multirate Design Example: Registers
3.1. Ethernet Multirate Design Example: Functional Description x
3.1.1. Ethernet Multirate Design Example: Simulation Testbench 3.1.2. Ethernet Multirate Hardware Design Example
4. Detailed Description for PMA/FEC Direct PHY Multirate Design Example x
4.1. PMA/FEC Direct PHY Multirate Design Example: Functional Description 4.2. PMA/FEC Direct PHY Multirate Design Example: Registers
4.1. PMA/FEC Direct PHY Multirate Design Example: Functional Description x
4.1.1. PMA/FEC Direct PHY Multirate Design Example: Simulation Testbench 4.1.2. PMA/FEC Direct PHY Multirate Hardware Design Example
5. Detailed Description for Ethernet to CPRI Design Example x
5.1. Ethernet to CPRI Design Example: Functional Description
5.1. Ethernet to CPRI Design Example: Functional Description x
5.1.1. Ethernet to CPRI Dynamic Reconfiguration Design Example: Simulation Testbench
1. Quick Start Guide
2. Detailed Description for CPRI Multirate Design Example
3. Detailed Description for Ethernet Multirate Design Example
4. Detailed Description for PMA/FEC Direct PHY Multirate Design Example
5. Detailed Description for Ethernet to CPRI Design Example
6. F-Tile Dynamic Reconfiguration Design Example User Guide Archives
7. Document Revision History for F-Tile Dynamic Reconfiguration Design Example User Guide

2.1.2. CPRI Multirate Hardware Design Example

Figure 8. CPRI Multirate Hardware Design Example Block Diagram

In the hardware design example, the reset, status, and control signals from packet clients, F-Tile CPRI PHY Multirate Intel® FPGA IP, and F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP in the example design are connected to In-System Sources and Probes IPs (ISSP). The hardware test scripts open service to the ISSP to read and drive the values. A JTAG host is instantiated to access the Avalon® memory-mapped interfaces.

Hardware Flow for Design Example:
  1. Enable the packet round-trip measurement.
    • Perform the deterministic latency test flow.
    • Print the deterministic latency data to det_latency.log file.
  2. Power up the CPRI PHY Multirate IP DUT based on profile 0 (24G RSFEC).
  3. Initialize the testbench variables based on power-up profile. The variables are:
    • cpri_speed: To indicate the speed of the current profile.
    • enable_rsfec: To indicate whether RS-FEC is enabled or disabled for the current profile.
    • current_dr_profile: To indicate the ID of the current profile.
  4. Perform dynamic reconfiguration.
  5. Check the testbench error flag and determine whether testbench passed or failed. This error flag is set to 1 if there is any error after dynamic reconfiguration traffic tests.
For customization, you can modify the DR_TRANSITION array variable in src or parameter file to configure test flow. Profile ID is passed into Dynamic Reconfiguration IP to configure the intended dynamic reconfiguration task.
  • DR_TRANSITION: Intended dynamic reconfiguration sequence array. The size of this array variable determines the number of dynamic reconfiguration to be performed.
For example, you want to achieve this Dynamic Reconfiguration sequence: 24G RS-FEC > 10G > 4.9G. The variables changes are: 
set DR_TRANSITION(0)   "10G"
set DR_TRANSITION(1)   " 4P9G"
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