F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP Release Notes

ID 710468
Date 7/08/2024
Public

1.2. F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP v9.0.0

Table 2.  v9.0.0 2024.04.01
Quartus® Prime Version Description Impact
24.1 Added support for Agilex™ 9 devices.
Added new parameter: Enable Auto-Negotiation and Link Training Optimized Simulation for Ethernet AN/LT example designs. When enabled, reduces the time required to simulate the design example.
Enabled hardware support for the Ethernet to CPRI Dynamic Reconfiguration Design Example (25G-1 PTP (with 1G PTP)) design.

Some Intel® FPGA IP products that previously included a Nios® II processor now use a Nios® V processor.

If you do not have a valid Nios® V license, you might receive an error message when you generate programming files for a design that includes these Intel® FPGA IP products.

For details and a workaround, refer to Why do I get an error in generating programming files and it shows as invalid license for Nios® V Processor for Intel® FPGA in the Quartus® Prime Pro Edition software version 24.1? in the Intel® FPGA Knowledge Base.