F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP Release Notes

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ID 710468
Date 11/04/2024
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1. F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP Release Notes
1. F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP Release Notes x
1.1. F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP v11.0.0 1.2. F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP v10.0.0 1.3. F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP v9.0.0 1.4. F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP v8.0.0 1.5. F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP v7.3.0 1.6. F-Tile Dynamic Reconfiguration Suite Intel FPGA IP v7.2.0 1.7. F-Tile Dynamic Reconfiguration Suite Intel FPGA IP v7.1.1 1.8. F-Tile Dynamic Reconfiguration Suite Intel FPGA IP v7.1.0 1.9. F-Tile Dynamic Reconfiguration Suite Intel FPGA IP v7.0.0 1.10. F-Tile Dynamic Reconfiguration Suite Intel FPGA IP v6.0.0 1.11. F-Tile Dynamic Reconfiguration Suite Intel FPGA IP v5.0.0 1.12. F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP v4.0.0 1.13. F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP User Guide Archives 1.14. F-Tile Dynamic Reconfiguration Design Example User Guide Archives
1. F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP Release Notes

1.1. F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP v11.0.0

Table 1.  v11.0.0 2024.11.04
Quartus® Prime Version Description Impact
24.3 Added Select Clock parameter in the Example Design tab. When enabled, allows you to set the frequency of the OSC_CLK_1 pin to match your board design or development kit.
Added User Logic block to the Ethernet design examples which enable Auto Negotiation and Link Training (AN/LT). Enables the real-time execution of DR flow from within the design example to meet the AN/LT requirements.
The Ethernet Multirate with Auto-Negotiation and Link Training Enabled via Dynamic Reconfiguration is currently undergoing hardware validation. Do not use this feature in a production design. —
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