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1.1. F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP v11.0.0
1.2. F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP v10.0.0
1.3. F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP v9.0.0
1.4. F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP v8.0.0
1.5. F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP v7.3.0
1.6. F-Tile Dynamic Reconfiguration Suite Intel FPGA IP v7.2.0
1.7. F-Tile Dynamic Reconfiguration Suite Intel FPGA IP v7.1.1
1.8. F-Tile Dynamic Reconfiguration Suite Intel FPGA IP v7.1.0
1.9. F-Tile Dynamic Reconfiguration Suite Intel FPGA IP v7.0.0
1.10. F-Tile Dynamic Reconfiguration Suite Intel FPGA IP v6.0.0
1.11. F-Tile Dynamic Reconfiguration Suite Intel FPGA IP v5.0.0
1.12. F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP v4.0.0
1.13. F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP User Guide Archives
1.14. F-Tile Dynamic Reconfiguration Design Example User Guide Archives
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Ixiasoft
1.6. F-Tile Dynamic Reconfiguration Suite Intel FPGA IP v7.2.0
Quartus® Prime Version | Description | Impact |
---|---|---|
23.2 | Added hardware support for the following design example variant:
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— |
Added a new design example variant: Ethernet with PTP to CPRI (with 1GE PTP). | Design example can be generated for compilation and simulation only. The current release does not provide hardware support. | |
Added Ethernet ANLT DR support for the Ethernet base variants. | — |