F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP Release Notes

Download PDF
ID 710468
Date 4/03/2024
Public
Document Table of Contents
Document Table of Contents x
1. F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP Release Notes
1. F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP Release Notes x
1.1. F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP v9.0.0 1.2. F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP v8.0.0 1.3. F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP v7.3.0 1.4. F-Tile Dynamic Reconfiguration Suite Intel FPGA IP v7.2.0 1.5. F-Tile Dynamic Reconfiguration Suite Intel FPGA IP v7.1.1 1.6. F-Tile Dynamic Reconfiguration Suite Intel FPGA IP v7.1.0 1.7. F-Tile Dynamic Reconfiguration Suite Intel FPGA IP v7.0.0 1.8. F-Tile Dynamic Reconfiguration Suite Intel FPGA IP v6.0.0 1.9. F-Tile Dynamic Reconfiguration Suite Intel FPGA IP v5.0.0 1.10. F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP v4.0.0 1.11. F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP User Guide Archives 1.12. F-Tile Dynamic Reconfiguration Design Example User Guide Archives
1. F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP Release Notes

1.3. F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP v7.3.0

Table 3.  v7.3.0 2023.10.02
Quartus® Prime Version Description Impact
23.3 Removed Include NIOS parameter Dynamic reconfiguration is only supported via NIOS.
Expanded the NIOS data memory size parameter's selection range Enhances configurability of data memory size.
Removed requirement to explicitly define master clock channel via the .qsf assignment for dynamic reconfiguration Quartus® Prime automatically selects system PLL/2 clock for dynamic reconfiguration.
For generated design examples, updated the choice of the targeted development kits to:
  • Agilex™ 7 FPGA I-Series Transceiver-SoC Development Kit DK-SI-AGI027FA
  • Agilex™ 7 FPGA I-Series Transceiver-SoC Development Kit DK-SI-AGI027FB
—
No hardware support for the following design example variant:
  • Ethernet 400G-8 with auto-negotiation and link training
This variant supports the Simulation, Compilation, and Timing Closure (SCT) only.
For Ethernet design examples that support the auto-negotiation and link training, only the F-Tile Auto-Negotiation and Link Training Intel® FPGA IP's parameter AN_CHAN=0 is supported. —
Level Two Title