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1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Agilex™ 7 F-Tile Devices
2. HDMI 2.1 Design Example (Support FRL = 1, Enable Active Video Protocol = None)
3. HDMI 2.1 Design Example with AXI4-stream Interface Enabled (Support FRL =1, Enable Active Video Protocol = AXIS-VVP Full)
4. Document Revision History for the F-Tile HDMI Intel® FPGA IP Design Example User Guide
2.1. Design Features
2.2. Hardware and Software Requirements
2.3. HDMI 2.1 RX-TX Retransmit Design Block Diagram
2.4. Design Parameters
2.5. Design Components
2.6. Design Software Flow
2.7. Clocking Scheme
2.8. Interface Signals
2.9. Hardware Setup
2.10. Simulation Testbench
2.11. Debugging Features
3.7.1. HDMI 2.1 RX-TX Retransmit Design without Video Frame Buffer (Enable Active Video Protocol = AXIS-VVP Full, Video In and Out Use the Same Clock = ON)
3.7.2. HDMI 2.1 RX-TX Retransmit Design with Video Frame Buffer (Enable Active Video Protocol = AXIS-VVP Full, Video In and Out Use the Same = OFF)
3.7.3. Clock Details
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3.7.3. Clock Details
Clock | Signal Name | Description |
---|---|---|
RX CDR Reference Clock | fgt_refclk_frl fgt_refclk_tmds_rx
|
Reference to the RX CDR. Reference clock 0 is connected to 100 MHz for FRL. Reference clock 1 is connected to the RX TMDS clock from the HDMI sink connector. |
RX PHY Clock Out | rx_sysclk_div2 rx_clk |
Two output clocks from the RX transceiver. Refer to the Clocking Schemes table for details. |
RX FRL Clock | rx_frl_clk | FRL clock to the RX core. Refer to HDMI IP Core User Guide Section 5.5 FRL Clocking Scheme for the FRL clock frequency for each FRL rate. |
RX Video Clock | rx_vid_clk | Video clock to the RX core. The clock runs at a fixed frequency of 225 MHz. |
TX PLL Refclk | fgt_refclk_frl fgt_refclk_tmds_tx |
Reference clock to the transceiver PLL. For FRL, this is a fixed 100 MHZ clock. For TMDS, the clock frequency follows the frequency of TMDS clock. |
TX PHY Clock Out | tx_sysclk_div2 tx_clk |
There are two output clocks from the TX transceiver. Refer to the Clocking Schemes table for details. |
TX FRL Clock | tx_frl_clk | FRL clock to the TX core. Refer to HDMI IP Core User Guide Section 5.5 FRL Clocking Scheme for the FRL clock frequency for each FRL rate. |
TX Video Clock | tx_vid_clk | Video clock to the TX core. In the RX-TX direct retransmit design without video frame buffer design, the clock runs at a fixed frequency of 225 MHz. In the RX-TX retransmit with video frame buffer design, the video clock is generated from a programmable oscillator at the frequency described in section Set TX Video Clock. TX video clock and TX PLL Refclk need to be driven from the same clock oscillator. |
Management Clock | mgmt_clk | A free-running 100 MHz clock for these components:
|
System PLL Refclk | systempll_clk | Reference clock to the System PLL block. The clock only supports 100 MHz frequency. |
EMIF Refclk | mem_pll_ref_clk | Reference clock to External Memory Interface. This clock is 166.67 MHz in this design. |