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1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Agilex™ 7 F-Tile Devices
2. HDMI 2.1 Design Example (Support FRL = 1, Enable Active Video Protocol = None)
3. HDMI 2.1 Design Example with AXI4-stream Interface Enabled (Support FRL =1, Enable Active Video Protocol = AXIS-VVP Full)
4. Document Revision History for the F-Tile HDMI Intel® FPGA IP Design Example User Guide
2.1. Design Features
2.2. Hardware and Software Requirements
2.3. HDMI 2.1 RX-TX Retransmit Design Block Diagram
2.4. Design Parameters
2.5. Design Components
2.6. Design Software Flow
2.7. Clocking Scheme
2.8. Interface Signals
2.9. Hardware Setup
2.10. Simulation Testbench
2.11. Debugging Features
3.7.1. HDMI 2.1 RX-TX Retransmit Design without Video Frame Buffer (Enable Active Video Protocol = AXIS-VVP Full, Video In and Out Use the Same Clock = ON)
3.7.2. HDMI 2.1 RX-TX Retransmit Design with Video Frame Buffer (Enable Active Video Protocol = AXIS-VVP Full, Video In and Out Use the Same = OFF)
3.7.3. Clock Details
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2.1. Design Features
The HDMI 2.1 design example in FRL mode supports the following features:
- Instantiates FIFO buffers to perform a direct HDMI video stream passthrough between the HDMI 2.1 sink and source.
- Includes HDMI RX and TX instances.
- Negotiates the FRL rate between the sink connected to TX and the source connected to RX. The design passes through the EDID from the external sink to the on-board RX in default configuration. The Nios® V processor negotiates the link based on the capability of the sink connected to TX. You can also toggle the user_dipsw on-board switch to manually control the TX and RX FRL capabilities.
- Includes several debugging features.
- HDMI configuration of:
- 8 pixel-in-parallel in video domain (FRL)
- 2 pixel-in-parallel in video domain (TMDS)
- 8 symbols per clock in FRL domain
- FRL and TMDS modes
- Display Stream Compression (DSC) Passthrough mode (enabled by default when DSC source is detected)
- EDID passthrough mode only
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