F-Tile HDMI Intel® FPGA IP Design Example User Guide

ID 709314
Date 6/06/2024
Public
Document Table of Contents

2.1. Design Features

The HDMI 2.1 design example in FRL mode supports the following features:
  • Instantiates FIFO buffers to perform a direct HDMI video stream passthrough between the HDMI 2.1 sink and source.
  • Includes HDMI RX and TX instances.
  • Negotiates the FRL rate between the sink connected to TX and the source connected to RX. The design passes through the EDID from the external sink to the on-board RX in default configuration. The Nios® V processor negotiates the link based on the capability of the sink connected to TX. You can also toggle the user_dipsw on-board switch to manually control the TX and RX FRL capabilities.
  • Includes several debugging features.
  • HDMI configuration of:
    • 8 pixel-in-parallel in video domain (FRL)
    • 2 pixel-in-parallel in video domain (TMDS)
    • 8 symbols per clock in FRL domain
  • FRL and TMDS modes
  • Display Stream Compression (DSC) Passthrough mode (enabled by default when DSC source is detected)
  • EDID passthrough mode only