F-Tile HDMI Intel® FPGA IP Design Example User Guide

ID 709314
Date 6/06/2024
Public
Document Table of Contents

3.10. Design Limitation (AXI/CV)

The HDMI 2.1 Design Example has seen the following critical warnings during compilation:
u_hdmi_rx_top|gxb_rx_inst|u_rx_phy_50|rx_phy_1p500g|dphy_hip_inst|persystem0.perxcvr0.fgt.rx_ux.x_bb_f_ux_rx did not set the following parameters
u_hdmi_rx_top|gxb_rx_inst|u_rx_phy_50|rx_phy_1p500g|dphy_hip_inst|persystem1.perxcvr0.fgt.rx_ux.x_bb_f_ux_rx did not set the following parameters
u_hdmi_rx_top|gxb_rx_inst|u_rx_phy_50|rx_phy_1p500g|dphy_hip_inst|persystem2.perxcvr0.fgt.rx_ux.x_bb_f_ux_rx did not set the following parameters
u_hdmi_rx_top|gxb_rx_inst|u_rx_phy_50|rx_phy_1p500g|dphy_hip_inst|persystem3.perxcvr0.fgt.rx_ux.x_bb_f_ux_rx did not set the following parameters
u_hdmi_rx_top|gxb_rx_inst|u_rx_phy_31|rx_phy_3p400g|dphy_hip_inst|persystem0.perxcvr0.fgt.rx_ux.x_bb_f_ux_rx did not set the following parameters
u_hdmi_rx_top|gxb_rx_inst|u_rx_phy_31|rx_phy_3p400g|dphy_hip_inst|persystem1.perxcvr0.fgt.rx_ux.x_bb_f_ux_rx did not set the following parameters
u_hdmi_rx_top|gxb_rx_inst|u_rx_phy_31|rx_phy_3p400g|dphy_hip_inst|persystem2.perxcvr0.fgt.rx_ux.x_bb_f_ux_rx did not set the following parameters
u_hdmi_rx_top|gxb_rx_inst|u_rx_phy_31|rx_phy_3p400g|dphy_hip_inst|persystem3.perxcvr0.fgt.rx_ux.x_bb_f_ux_rx did not set the following parameters
u_hdmi_rx_top|gxb_rx_inst|u_rx_phy_47|rx_phy_1p800g|dphy_hip_inst|persystem0.perxcvr0.fgt.rx_ux.x_bb_f_ux_rx did not set the following parameters
u_hdmi_rx_top|gxb_rx_inst|u_rx_phy_47|rx_phy_1p800g|dphy_hip_inst|persystem1.perxcvr0.fgt.rx_ux.x_bb_f_ux_rx did not set the following parameters

These critical warnings can be safely ignored.

For more information regarding the above critical warnings, refer to the Configurable Intel Quartus Prime Software Settings chapter in the F-Tile Architecture and PMA and FEC Direct PHY IP User Guide.