F-Tile HDMI Intel® FPGA IP Design Example User Guide

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ID 709314
Date 6/06/2024
Public
Document Table of Contents
Document Table of Contents x
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Agilex™ 7 F-Tile Devices 2. HDMI 2.1 Design Example (Support FRL = 1, Enable Active Video Protocol = None) 3. HDMI 2.1 Design Example with AXI4-stream Interface Enabled (Support FRL =1, Enable Active Video Protocol = AXIS-VVP Full) 4. Document Revision History for the F-Tile HDMI Intel® FPGA IP Design Example User Guide
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Agilex™ 7 F-Tile Devices x
1.1. Directory Structure 1.2. Generating the Design 1.3. Simulating the Design 1.4. Compiling and Testing the Design
2. HDMI 2.1 Design Example (Support FRL = 1, Enable Active Video Protocol = None) x
2.1. Design Features 2.2. Hardware and Software Requirements 2.3. HDMI 2.1 RX-TX Retransmit Design Block Diagram 2.4. Design Parameters 2.5. Design Components 2.6. Design Software Flow 2.7. Clocking Scheme 2.8. Interface Signals 2.9. Hardware Setup 2.10. Simulation Testbench 2.11. Debugging Features
2.3. HDMI 2.1 RX-TX Retransmit Design Block Diagram x
2.3.1. Creating RX-Only or TX-Only Designs
2.4. Design Parameters x
2.4.1. IP Parameters 2.4.2. HDMI Intel® FPGA IP Design Example Parameters
2.5. Design Components x
2.5.1. HDMI TX Components 2.5.2. HDMI RX Components 2.5.3. Top-Level Common Blocks
2.5.1. HDMI TX Components x
2.5.1.1. TX PHY Adapter
2.5.1.1. TX PHY Adapter x
2.5.1.1.1. FRL and TMDS
2.5.2. HDMI RX Components x
2.5.2.1. RX PHY Adapter
2.11. Debugging Features x
2.11.1. Software Debug Message 2.11.2. SCDC Information from Sink Connected to TX 2.11.3. Clock Frequency Measurement
3. HDMI 2.1 Design Example with AXI4-stream Interface Enabled (Support FRL =1, Enable Active Video Protocol = AXIS-VVP Full) x
3.1. Design Features 3.2. Hardware and Software Requirements 3.3. HDMI 2.1 RX-TX Retransmit Design Block Diagrams 3.4. Design Parameters 3.5. Design Components 3.6. Design Software Flow 3.7. Clocking Scheme 3.8. Interface Signals 3.9. Hardware Setup 3.10. Design Limitation (AXI/CV)
3.3. HDMI 2.1 RX-TX Retransmit Design Block Diagrams x
3.3.1. HDMI 2.1 RX-TX Direct Retransmit Design Block Diagram (Without Video Frame Buffer) 3.3.2. HDMI 2.1 RX-TX Retransmit Design Block Diagram (With Video Frame Buffer)
3.4. Design Parameters x
3.4.1. HDMI RX Direction 3.4.2. HDMI TX Direction
3.6. Design Software Flow x
3.6.1. Configure Redriver Setting 3.6.2. Initialize TX Path 3.6.3. Initialize RX Path 3.6.4. Initialize HDMI TX Register 3.6.5. Wait for RX Path Ready 3.6.6. TX Reconfiguration and Link Training 3.6.7. Set TX Video Clock 3.6.8. Set AXI2CV Configuration 3.6.9. HDMI TX Transmit Video
3.7. Clocking Scheme x
3.7.1. HDMI 2.1 RX-TX Retransmit Design without Video Frame Buffer (Enable Active Video Protocol = AXIS-VVP Full, Video In and Out Use the Same Clock = ON) 3.7.2. HDMI 2.1 RX-TX Retransmit Design with Video Frame Buffer (Enable Active Video Protocol = AXIS-VVP Full, Video In and Out Use the Same = OFF) 3.7.3. Clock Details
3.8. Interface Signals x
3.8.1. Platform Design System
3.9. Hardware Setup x
3.9.1. Supporting Additional Video Resolutions
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Agilex™ 7 F-Tile Devices
2. HDMI 2.1 Design Example (Support FRL = 1, Enable Active Video Protocol = None)
3. HDMI 2.1 Design Example with AXI4-stream Interface Enabled (Support FRL =1, Enable Active Video Protocol = AXIS-VVP Full)
4. Document Revision History for the F-Tile HDMI Intel® FPGA IP Design Example User Guide

1.4. Compiling and Testing the Design

Figure 5. Design Compilation and Hardware Flow
To compile and run a demonstration test on the hardware example design, follow these steps:
  1. Ensure hardware example design generation is complete.
  2. Launch the Quartus® Prime Pro Edition software and open the .qpf file. Directory location:
    • project directory/quartus/agx_hdmi21_frl_demo.qpf, or
    • project directory/quartus/agx_hdmi21_frl_axi_demo.qpf
  3. Click Processing > Start Compilation.
  4. After successful compilation, a .sof file is generated in your specified directory.
  5. Set up the hardware and power up the Intel FPGA board.
  6. Set up factory switch settings according to the different design example variants, as described in the table below.
    Table 6.  Factory Switch Settings according to Design Example Variant
    Clock Input MUX_SEL Switch Design Variant
    Enable Active Video = None Enable Active Video Protocol = AXIS-VVP Full, Video in and out use the same clock = OFF Enable Active Video Protocol = AXIS-VVP Full, Video in and out use the same clock = ON
    SI5332E OUT3 MUX_SEL8 S4[4] /MUX_DIP_SW11 Not Applicable ON ON
    SI5391B OUT0 MUX_SEL10 S23[1]/MUX_DIP_SW4 OFF OFF OFF
    SI5391B OUT6 MUX_SEL11 S23[2]/MUX_DIP_SW5 ON ON Not Applicable
    SI5391B OUT9 MUX_SEL12 S23[3]/MUX_DIP_SW6 ON ON ON
    SI5391B OUT5 MUX_SEL14 S23[4]/MUX_DIP_SW7 ON ON ON
  7. Perform the following settings. Open the Clock Controller editor and set the clock frequency in the Si5391-B tab.
    Note: Make sure Clock Controller displays Connected to the target before proceeding with the clock settings. If Clock Controller displays a different message, exit and reopen Clock Controller. In a successful clock setting, the F_vco displays a certain clock frequency as shown in the following figures.
    1. For HDMI 2.1 design example with Support FRL = 1 and Enable Active Video Protocol = None, set OUT6 frequency to 100.00 MHz.
      Figure 6. HDMI 2.1 Design Example with Support FRL =1 and Enable Active Video Protocol = None
      Note: The design uses OUT6. However, Intel recommends that you set all output clocks to 100 MHz so that the oscillator can generate the exact 100 MHz clock.
    2. For HDMI 2.1 design example with Support FRL = 1, Enable Active Video Protocol = AXIS-VVP Full, and Video in and out use the same clock = ON, set OUT9 frequency to 100.00 MHz.
      Figure 7. HDMI 2.1 Design Example with Support FRL =1, Enable Active Video Protocol = AXIS-VVP Full, and Video In and Out Use the Same Clock = ON
      Note: The design uses OUT9. However, Intel recommends that you set all output clocks to 100 MHz so that the oscillator can generate the exact 100 MHz clock.
    3. For HDMI 2.1 design example with Support FRL = 1, Enable Active Video Protocol = AXIS-VVP Full, and Video in and out use the same clock = OFF, set Set OUT6 and OUT9 frequencies to 100.00 MHz.
      Figure 8. HDMI 2.1 Design Example with Support FRL =1, Enable Active Video Protocol = AXIS-VVP Full, and Video In and Out Use the Same Clock = OFF
      Note: The design uses OUT6 and OUT9. However, Intel recommends that you set all output clocks to 100 MHz so that the oscillator can generate the exact 100 MHz clock.
  8. Configure the selected device on the development board using the generated .sof file (Tools > Programmer).
    • HDMI 2.1 design example with Support FRL enabled:
      • project directory/quartus/output_files/agx_hdmi21_frl_demo.sof
  9. If you have made changes to the software files or within the IP Parameter Editor, you need to run the build_niosv_sw.py script to rebuild the software. Run the script using Nios® V command shell with a command "quartus_py build_niosv_sw.py".
  10. Download the software .elf file using the Nios V Terminal.
    • Enable Active Video Protocol = None
      • Download .elf file: niosv-download <project directory> /software/tx_control/tx_control.elf -g -r -i 1
      • Run Nios terminal: juart-terminal -i 1
    • Enable Active Video Protocol = AXIS-VVP Full
      • Download .elf file: niosv-download <project directory> / software/tx_control/tx_control.elf -g -r -i 0
      • Run Nios terminal: juart-terminal -i 0
    Note: This step is required because the software DEBUG_MODE is enabled by default.
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