F-Tile HDMI Intel® FPGA IP Design Example User Guide

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ID 709314
Date 8/15/2023
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Document Table of Contents
Document Table of Contents x
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel Agilex® 7 F-tile Devices 2. HDMI 2.1 Design Example (Support FRL = 1, Enable Active Video Protocol = None) 3. HDMI 2.1 Design Example with AXI4-stream Interface Enabled (Support FRL =1, Enable Active Video Protocol = AXIS-VVP Full) 4. Document Revision History for the F-Tile HDMI Intel® FPGA IP Design Example User Guide
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel Agilex® 7 F-tile Devices x
1.1. Directory Structure 1.2. Generating the Design 1.3. Simulating the Design 1.4. Compiling and Testing the Design
2. HDMI 2.1 Design Example (Support FRL = 1, Enable Active Video Protocol = None) x
2.1. Design Features 2.2. Hardware and Software Requirements 2.3. HDMI 2.1 RX-TX Retransmit Design Block Diagram 2.4. Design Parameters 2.5. Design Components 2.6. Design Software Flow 2.7. Clocking Scheme 2.8. Interface Signals 2.9. Hardware Setup 2.10. Simulation Testbench 2.11. Debugging Features
2.3. HDMI 2.1 RX-TX Retransmit Design Block Diagram x
2.3.1. Creating RX-Only or TX-Only Designs
2.4. Design Parameters x
2.4.1. IP Parameters 2.4.2. HDMI Intel® FPGA IP Design Example Parameters
2.5. Design Components x
2.5.1. HDMI TX Components 2.5.2. HDMI RX Components 2.5.3. Top-Level Common Blocks
2.5.1. HDMI TX Components x
2.5.1.1. TX PHY Adapter
2.5.1.1. TX PHY Adapter x
2.5.1.1.1. FRL and TMDS
2.5.2. HDMI RX Components x
2.5.2.1. RX PHY Adapter
2.11. Debugging Features x
2.11.1. Software Debug Message 2.11.2. SCDC Information from Sink Connected to TX 2.11.3. Clock Frequency Measurement
3. HDMI 2.1 Design Example with AXI4-stream Interface Enabled (Support FRL =1, Enable Active Video Protocol = AXIS-VVP Full) x
3.1. Design Features 3.2. Hardware and Software Requirements 3.3. HDMI 2.1 RX-TX Retransmit Design Block Diagrams 3.4. Design Parameters 3.5. Design Components 3.6. Design Software Flow 3.7. Clocking Scheme 3.8. Interface Signals 3.9. Hardware Setup 3.10. Design Limitation (AXI/CV)
3.3. HDMI 2.1 RX-TX Retransmit Design Block Diagrams x
3.3.1. HDMI 2.1 RX-TX Direct Retransmit Design Block Diagram (Without Video Frame Buffer) 3.3.2. HDMI 2.1 RX-TX Retransmit Design Block Diagram (With Video Frame Buffer)
3.4. Design Parameters x
3.4.1. HDMI RX Direction 3.4.2. HDMI TX Direction
3.6. Design Software Flow x
3.6.1. Configure Redriver Setting 3.6.2. Initialize TX Path 3.6.3. Initialize RX Path 3.6.4. Initialize HDMI TX Register 3.6.5. Wait for RX Path Ready 3.6.6. TX Reconfiguration and Link Training 3.6.7. Set TX Video Clock 3.6.8. Set AXI2CV Configuration 3.6.9. HDMI TX Transmit Video
3.7. Clocking Scheme x
3.7.1. HDMI 2.1 RX-TX Retransmit Design without Video Frame Buffer (Enable Active Video Protocol = AXIS-VVP Full, Video In and Out Use the Same Clock = ON) 3.7.2. HDMI 2.1 RX-TX Retransmit Design with Video Frame Buffer (Enable Active Video Protocol = AXIS-VVP Full, Video In and Out Use the Same = OFF) 3.7.3. Clock Details
3.8. Interface Signals x
3.8.1. Platform Design System
3.9. Hardware Setup x
3.9.1. Supporting Additional Video Resolutions
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel Agilex® 7 F-tile Devices
2. HDMI 2.1 Design Example (Support FRL = 1, Enable Active Video Protocol = None)
3. HDMI 2.1 Design Example with AXI4-stream Interface Enabled (Support FRL =1, Enable Active Video Protocol = AXIS-VVP Full)
4. Document Revision History for the F-Tile HDMI Intel® FPGA IP Design Example User Guide

3.8.1. Platform Design System

Table 29.  Interface Signals for Platform Design System
Signal Direction Width Description
cpu_clk_in_clk_clk Input 1 CPU clock. The frequency is 100 Mhz
cpu_rst_in_reset_reset Input 1 CPU reset
redriver_i2c_master_sda_in Input 1 I2C master interface to configure the external redriver setting
redriver_i2c_master_scl_in Input 1
redriver_i2c_master_sda_oe Output 1
redriver_i2c_master_scl_oe Output 1
txclk_i2c_master_sda_in Input 1 I2C master interface to configure the programmable oscillator to output TX video clock for RX-TX retransmit without video frame buffer design
txclk_i2c_master_scl_in Input 1
txclk_i2c_master_sda_oe Output 1
txclk_i2c_master_scl_oe Output 1
hdmi_rx_i2c_clk_clk Input 1 Clock input for DDC and SCDC interface. This clock is 100 Mhz
hdmi_rx_i2c_interface_scl Input 1 HDMI RX DDC and SCDC interface
hdmi_rx_i2c_interface_sda Input 1
hdmi_rx_hpd_interface_in_5v_power Input 1 HDMI RX 5V detect and hotplug detect. Refer to the Sink Interfaces section in HDMI Intel FPGA IP User Guide for more information
hdmi_rx_hpd_interface_hpd Output 1
hdmi_rx_av_mm_aux_out_aux_pkt_data Output 72

Auxiliary Memory Interface.

Refer to the Sink Interfaces section in HDMI Intel FPGA IP User Guide for more information

hdmi_rx_av_mm_aux_out_aux_pkt_addr Output 7
hdmi_rx_av_mm_aux_out_aux_pkt_wr Output 1
hdmi_tx_hpd_interface_hpd Input 1 HDMI TX Hot plug Detect interface
hdmi_tx_i2c_interface_scl Input 1 HDMI TX DDC and SCDC interface
hdmi_tx_i2c_interface_sda Input 1
hdmi_tx_audio_interface_audio_mute Input 1

HDMI TX Audio Mute control.

0 = Audio unmute

1 = Audio mute, audio data ignored
ddr4_emif_local_reset_req_local_reset_req Input 1

External Memory IP Interface (EMIF) for DDR4.

Refer to Section 4.1 of Intel Agilex® 7 EMIF IP Interface and Signal Descriptions of External Memory Interface Intel Agilex® 7 FPGA IP User Guide for more details.

Note: Only available when With Video Frame Buffer Design is selected.
ddr4_emif_local_reset_status_local_reset_done Output 1
ddr4_emif_pll_ref_clk_clk Input 1
ddr4_emif_oct_oct_rzqin Input 1
ddr4_emif_mem_mem_ck Output 1
ddr4_emif_mem_mem_ck_n Output 1
ddr4_emif_mem_mem_a Output 17
ddr4_emif_mem_mem_act_n Output 1
ddr4_emif_mem_mem_ba Output 2
ddr4_emif_mem_mem_bg Output 1
ddr4_emif_mem_mem_cke Output 1
ddr4_emif_mem_mem_cs_n Output 1
ddr4_emif_mem_mem_odt Output 1
ddr4_emif_mem_mem_reset_n Output 1
ddr4_emif_mem_mem_par Output 1
ddr4_emif_mem_mem_alert_n Input 1
ddr4_emif_mem_mem_dqs Input 9
ddr4_emif_mem_mem_dqs_n Input 9
ddr4_emif_mem_mem_dq Input 72
ddr4_emif_mem_mem_dbi_n Input 9
ddr4_emif_status_local_cal_success Output 1
ddr4_emif_status_local_cal_fail Output 1
dr_f_i_rst_n_reset_n Input 1 Dynamic Reconfig IP interface
dr_f_o_dr_curr_profile_id_o_dr_curr_profile_id Output 15
dr_f_o_dr_in_progress_o_dr_in_progress Output 1
dr_f_o_dr_error_status_o_dr_error_status Output 1
intel_hdmi_rx_phy_i2c_clk_clk Input 1 HDMI RX Transceiver Repackage Interface
intel_hdmi_rx_phy_rx_serial_data_wire1 Input 4
intel_hdmi_rx_phy_rx_serial_data_n_wire1 Input 4
intel_hdmi_rx_phy_phy_interface_hdmi_5v_detect_n Input 1
intel_hdmi_rx_phy_phy_interface_rx_5v_detect Output 1
intel_hdmi_rx_phy_phy_interface_device_ready Input 1
intel_hdmi_tx_phy_tx_serial_data_wire1 Output 4 HDMI TX Transceiver Repackage Interface
intel_hdmi_tx_phy_tx_serial_data_n_wire1 Output 4
intel_hdmi_tx_phy_tx_vid_clk_in_clk Input 1
intel_hdmi_tx_phy_phy_interface_device_ready Input 1
pll_vidclk_refclk_clk Input 1 IOPLL interface for video clock
systemclk_f_out_systempll_synthlock_0_out_systempll_synthlock Output 1 Transceiver SystemPLL clock interface
systemclk_f_refclk_fgt_in_refclk_fgt_0 Input 1
systemclk_f_refclk_fgt_in_refclk_fgt_1 Input 1
systemclk_f_refclk_fgt_in_refclk_fgt_2 Input 1
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