F-Tile HDMI Intel® FPGA IP Design Example User Guide

ID 709314
Date 8/15/2023
Public

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1.4. Compiling and Testing the Design

Figure 5. Design Compilation and Hardware Flow
To compile and run a demonstration test on the hardware example design, follow these steps:
  1. Ensure hardware example design generation is complete.
  2. Launch the Intel® Quartus® Prime Pro Edition software and open the .qpf file. Directory location:
    • project directory/quartus/agx_hdmi21_frl_demo.qpf, or
    • project directory/quartus/agx_hdmi21_frl_axi_demo.qpf
  3. Click Processing > Start Compilation.
  4. After successful compilation, a .sof file generates in your specified directory.
  5. Set up the hardware and power up the Intel FPGA board.
  6. Set up factory switch settings according to the different design example variants, as described in the table below.
    Table 6.  Factory Switch Settings according to Design Example Variant
    Clock Input MUX_SEL Switch Design Variant
    Enable Active Video = None Enable Active Video Protocol = AXIS-VVP Full, Video in and out use the same clock = OFF Enable Active Video Protocol = AXIS-VVP Full, Video in and out use the same clock = ON
    SI5332E OUT3 MUX_SEL8 S4[4] /MUX_DIP_SW11 Not Applicable ON ON
    SI5391B OUT0 MUX_SEL10 S23[1]/MUX_DIP_SW4 OFF OFF OFF
    SI5391B OUT6 MUX_SEL11 S23[2]/MUX_DIP_SW5 ON ON Not Applicable
    SI5391B OUT9 MUX_SEL12 S23[3]/MUX_DIP_SW6 ON ON ON
    SI5391B OUT5 MUX_SEL14 S23[4]/MUX_DIP_SW7 ON ON ON
  7. Perform the following settings. Open the Clock Controller editor and set the clock frequency in Si5391-B tab.
    Note: Make sure Clock Controller displays Connected to the target before proceeding with the clock settings. If Clock Controller displays a different message, exit and reopen Clock Controller. In a successful clock setting, the F_vco displays a certain clock frequency as shown in the following figures.
    1. For HDMI 2.1 design example with Support FRL = 1 and Enable Active Video Protocol = None, set OUT6 frequency to 100.00 MHz.
      Figure 6. HDMI 2.1 Design Example with Support FRL =1 and Enable Active Video Protocol = None
    2. For HDMI 2.1 design example with Support FRL = 1, Enable Active Video Protocol = AXIS-VVP Full, and Video in and out use the same clock = ON, set OUT9 frequency to 100.00 MHz.
      Figure 7. HDMI 2.1 Design Example with Support FRL =1, Enable Active Video Protocol = AXIS-VVP Full, and Video In and Out Use the Same Clock = ON
    3. For HDMI 2.1 design example with Support FRL = 1, Enable Active Video Protocol = AXIS-VVP Full, and Video in and out use the same clock = OFF, set Set OUT6 and OUT9 frequencies to 100.00 MHz.
      Figure 8. HDMI 2.1 Design Example with Support FRL =1, Enable Active Video Protocol = AXIS-VVP Full, and Video In and Out Use the Same Clock = OFF
  8. Configure the selected device on the development board using the generated .sof file (Tools > Programmer).
    • HDMI 2.1 design example with Support FRL enabled:
      • project directory/quartus/output_files/agx_hdmi21_frl_demo.sof
  9. If you have made changes on the software files or within the IP Parameter Editor, you need to run the build_sw.sh script to rebuild the software.
  10. Download the software .elf file using the Nios2 Terminal.
    • Enable Active Video Protocol = None
      • Download .elf file: nios2-download <project directory> /software/tx_control/tx_control.elf -g -r -i 1
      • Run Nios terminal: nios2-terminal -i 1
    • Enable Active Video Protocol = AXIS-VVP Full
      • Download .elf file: nios2-download <project directory> / software/hdmi21_demo_app/hdmi21_demo.elf -g -r -i 0
      • Run Nios terminal: nios2-terminal -i 0
    Note: This step is required because the software DEBUG_MODE is enabled by default.