F-Tile HDMI Intel® FPGA IP Design Example User Guide

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ID 709314
Date 8/15/2023
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Document Table of Contents
Document Table of Contents x
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel Agilex® 7 F-tile Devices 2. HDMI 2.1 Design Example (Support FRL = 1, Enable Active Video Protocol = None) 3. HDMI 2.1 Design Example with AXI4-stream Interface Enabled (Support FRL =1, Enable Active Video Protocol = AXIS-VVP Full) 4. Document Revision History for the F-Tile HDMI Intel® FPGA IP Design Example User Guide
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel Agilex® 7 F-tile Devices x
1.1. Directory Structure 1.2. Generating the Design 1.3. Simulating the Design 1.4. Compiling and Testing the Design
2. HDMI 2.1 Design Example (Support FRL = 1, Enable Active Video Protocol = None) x
2.1. Design Features 2.2. Hardware and Software Requirements 2.3. HDMI 2.1 RX-TX Retransmit Design Block Diagram 2.4. Design Parameters 2.5. Design Components 2.6. Design Software Flow 2.7. Clocking Scheme 2.8. Interface Signals 2.9. Hardware Setup 2.10. Simulation Testbench 2.11. Debugging Features
2.3. HDMI 2.1 RX-TX Retransmit Design Block Diagram x
2.3.1. Creating RX-Only or TX-Only Designs
2.4. Design Parameters x
2.4.1. IP Parameters 2.4.2. HDMI Intel® FPGA IP Design Example Parameters
2.5. Design Components x
2.5.1. HDMI TX Components 2.5.2. HDMI RX Components 2.5.3. Top-Level Common Blocks
2.5.1. HDMI TX Components x
2.5.1.1. TX PHY Adapter
2.5.1.1. TX PHY Adapter x
2.5.1.1.1. FRL and TMDS
2.5.2. HDMI RX Components x
2.5.2.1. RX PHY Adapter
2.11. Debugging Features x
2.11.1. Software Debug Message 2.11.2. SCDC Information from Sink Connected to TX 2.11.3. Clock Frequency Measurement
3. HDMI 2.1 Design Example with AXI4-stream Interface Enabled (Support FRL =1, Enable Active Video Protocol = AXIS-VVP Full) x
3.1. Design Features 3.2. Hardware and Software Requirements 3.3. HDMI 2.1 RX-TX Retransmit Design Block Diagrams 3.4. Design Parameters 3.5. Design Components 3.6. Design Software Flow 3.7. Clocking Scheme 3.8. Interface Signals 3.9. Hardware Setup 3.10. Design Limitation (AXI/CV)
3.3. HDMI 2.1 RX-TX Retransmit Design Block Diagrams x
3.3.1. HDMI 2.1 RX-TX Direct Retransmit Design Block Diagram (Without Video Frame Buffer) 3.3.2. HDMI 2.1 RX-TX Retransmit Design Block Diagram (With Video Frame Buffer)
3.4. Design Parameters x
3.4.1. HDMI RX Direction 3.4.2. HDMI TX Direction
3.6. Design Software Flow x
3.6.1. Configure Redriver Setting 3.6.2. Initialize TX Path 3.6.3. Initialize RX Path 3.6.4. Initialize HDMI TX Register 3.6.5. Wait for RX Path Ready 3.6.6. TX Reconfiguration and Link Training 3.6.7. Set TX Video Clock 3.6.8. Set AXI2CV Configuration 3.6.9. HDMI TX Transmit Video
3.7. Clocking Scheme x
3.7.1. HDMI 2.1 RX-TX Retransmit Design without Video Frame Buffer (Enable Active Video Protocol = AXIS-VVP Full, Video In and Out Use the Same Clock = ON) 3.7.2. HDMI 2.1 RX-TX Retransmit Design with Video Frame Buffer (Enable Active Video Protocol = AXIS-VVP Full, Video In and Out Use the Same = OFF) 3.7.3. Clock Details
3.8. Interface Signals x
3.8.1. Platform Design System
3.9. Hardware Setup x
3.9.1. Supporting Additional Video Resolutions
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel Agilex® 7 F-tile Devices
2. HDMI 2.1 Design Example (Support FRL = 1, Enable Active Video Protocol = None)
3. HDMI 2.1 Design Example with AXI4-stream Interface Enabled (Support FRL =1, Enable Active Video Protocol = AXIS-VVP Full)
4. Document Revision History for the F-Tile HDMI Intel® FPGA IP Design Example User Guide

1.1. Directory Structure

The directories contain the generated files for the HDMI Intel® FPGA IP design example.
Figure 2. Directory Structure for the Design Example
Table 1.  Generated RTL Files
Folders Files/Subfolders
common clock_crosser.v
dcfifo_inst.v
edge_detector.sv
fifo.ip
output_buf_i2c.ip
test_pattern_gen.v
mr_rate_detect.v
tpg_data.ip
tx_dcfifo.v
dr dr.ip
gxb gxb_rx.v
gxb_tx.v
gxb/rx_phy rx_phy_3g.ip
rx_phy_6g.ip
rx_phy_8g.ip
rx_phy_10g.ip
rx_phy_12g.ip
rx_phy_0p300g - rx_phy_6g_tmds.ip
gxb/tx_phy data_converter_80to128.v
tx_phy_3g.ip
tx_phy_6g.ip
tx_phy_8g.ip
tx_phy_10g.ip
tx_phy_12g.ip
tx_phy_0p300g - tx_phy_6g_tmds.ip
gxb/sys_clk sys_clk.ip
hdmi_rx hdmi_rx.ip
hdmi_rx_top.v
Panasonic.hex
hdmi_tx hdmi_tx.ip
hdmi_tx_top.v
i2c_slave i2c_avl_mst_intf_gen.v
i2c_clk_cnt.v
i2c_condt_det.v
i2c_databuffer.v
i2c_rxshifter.v
i2c_slvfsm.v
i2c_spksupp.v
i2c_txout.v
i2c_txshifter.v
i2cslave_to_avlmm_bridge.v
pll pll_frl_rx.ip
pll_frl_tx.ip
pll_pixel.ip
pll_vidclk.ip
reconfig altera_xcvr_functions.sv
mr_compare.sv
mr_rate_detect.v
mr_rx_rate_detect_top.v
mr_rx_rcfg_ctrl.v
mr_rx_reconfig.v
mr_tx_rate_detect_top.v
mr_tx_rcfg_ctrl.v
mr_tx_reconfig.v
rcfg_array_streamer_iopll.sv
rcfg_array_streamer_rxphy.sv
rcfg_array_streamer_rxphy_xn.sv
rcfg_array_streamer_txphy.sv
rcfg_array_streamer_txphy_xn.sv
rcfg_array_streamer_txpll.sv
mr_compare_threshold_rxphy.sv
mr_compare_threshold_txphy.sv
rxtx_link altera_hdmi_hdr_infoframe.v
aux_mux.qsys
aux_retransmit.v
aux_src_gen.v
ext_aux_filter.v
rxtx_link.v
scfifo_vid.ip
sdc agx_hdmi2.sdc
jtag.sdc
Table 2.  Generated Simulation FilesRefer to the Simulation Testbench section for more information.
Folders Files
aldec /aldec.do
/rivierapro_setup.tcl
mentor /mentor.do
/msim_setup.tcl
synopsys /vcs/filelist.f
/vcs/vcs_setup.sh
/vcs/vcs_sim.sh
/vcsmx/synopsys_sim_setup
/vcsmx/vcsmx_setup.sh
/vcsmx/vcsmx_sim.sh
xcelium /cds.lib
/hdl.var
/xcelium_setup.sh
/xcelium_sim.sh
<cds_libs folder>
common /modelsim_files.tcl
/riviera_files.tcl
/vcs_files.tcl
/vcsmx_files.tcl
/xcelium_files.tcl
hdmi_rx /hdmi_rx.ip
/Panasonic.hex
hdmi_tx /hdmi_tx.ip
Table 3.  Generated Software Files
Folders Files
tx_control_src
Note: The tx_control folder also contains duplicates of these files.
global.h
hdmi_rx.c
hdmi_rx.h
hdmi_tx.c
hdmi_tx.h
hdmi_tx_read_edid.c
hdmi_tx_read_edid.h
intel_fpga_i2c.c
intel_fpga_i2c.h
main.c
pio_read_write.c
pio_read_write.h
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