F-Tile HDMI Intel® FPGA IP Design Example User Guide

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ID 709314
Date 8/15/2023
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Document Table of Contents
Document Table of Contents x
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel Agilex® 7 F-tile Devices 2. HDMI 2.1 Design Example (Support FRL = 1, Enable Active Video Protocol = None) 3. HDMI 2.1 Design Example with AXI4-stream Interface Enabled (Support FRL =1, Enable Active Video Protocol = AXIS-VVP Full) 4. Document Revision History for the F-Tile HDMI Intel® FPGA IP Design Example User Guide
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel Agilex® 7 F-tile Devices x
1.1. Directory Structure 1.2. Generating the Design 1.3. Simulating the Design 1.4. Compiling and Testing the Design
2. HDMI 2.1 Design Example (Support FRL = 1, Enable Active Video Protocol = None) x
2.1. Design Features 2.2. Hardware and Software Requirements 2.3. HDMI 2.1 RX-TX Retransmit Design Block Diagram 2.4. Design Parameters 2.5. Design Components 2.6. Design Software Flow 2.7. Clocking Scheme 2.8. Interface Signals 2.9. Hardware Setup 2.10. Simulation Testbench 2.11. Debugging Features
2.3. HDMI 2.1 RX-TX Retransmit Design Block Diagram x
2.3.1. Creating RX-Only or TX-Only Designs
2.4. Design Parameters x
2.4.1. IP Parameters 2.4.2. HDMI Intel® FPGA IP Design Example Parameters
2.5. Design Components x
2.5.1. HDMI TX Components 2.5.2. HDMI RX Components 2.5.3. Top-Level Common Blocks
2.5.1. HDMI TX Components x
2.5.1.1. TX PHY Adapter
2.5.1.1. TX PHY Adapter x
2.5.1.1.1. FRL and TMDS
2.5.2. HDMI RX Components x
2.5.2.1. RX PHY Adapter
2.11. Debugging Features x
2.11.1. Software Debug Message 2.11.2. SCDC Information from Sink Connected to TX 2.11.3. Clock Frequency Measurement
3. HDMI 2.1 Design Example with AXI4-stream Interface Enabled (Support FRL =1, Enable Active Video Protocol = AXIS-VVP Full) x
3.1. Design Features 3.2. Hardware and Software Requirements 3.3. HDMI 2.1 RX-TX Retransmit Design Block Diagrams 3.4. Design Parameters 3.5. Design Components 3.6. Design Software Flow 3.7. Clocking Scheme 3.8. Interface Signals 3.9. Hardware Setup 3.10. Design Limitation (AXI/CV)
3.3. HDMI 2.1 RX-TX Retransmit Design Block Diagrams x
3.3.1. HDMI 2.1 RX-TX Direct Retransmit Design Block Diagram (Without Video Frame Buffer) 3.3.2. HDMI 2.1 RX-TX Retransmit Design Block Diagram (With Video Frame Buffer)
3.4. Design Parameters x
3.4.1. HDMI RX Direction 3.4.2. HDMI TX Direction
3.6. Design Software Flow x
3.6.1. Configure Redriver Setting 3.6.2. Initialize TX Path 3.6.3. Initialize RX Path 3.6.4. Initialize HDMI TX Register 3.6.5. Wait for RX Path Ready 3.6.6. TX Reconfiguration and Link Training 3.6.7. Set TX Video Clock 3.6.8. Set AXI2CV Configuration 3.6.9. HDMI TX Transmit Video
3.7. Clocking Scheme x
3.7.1. HDMI 2.1 RX-TX Retransmit Design without Video Frame Buffer (Enable Active Video Protocol = AXIS-VVP Full, Video In and Out Use the Same Clock = ON) 3.7.2. HDMI 2.1 RX-TX Retransmit Design with Video Frame Buffer (Enable Active Video Protocol = AXIS-VVP Full, Video In and Out Use the Same = OFF) 3.7.3. Clock Details
3.8. Interface Signals x
3.8.1. Platform Design System
3.9. Hardware Setup x
3.9.1. Supporting Additional Video Resolutions
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel Agilex® 7 F-tile Devices
2. HDMI 2.1 Design Example (Support FRL = 1, Enable Active Video Protocol = None)
3. HDMI 2.1 Design Example with AXI4-stream Interface Enabled (Support FRL =1, Enable Active Video Protocol = AXIS-VVP Full)
4. Document Revision History for the F-Tile HDMI Intel® FPGA IP Design Example User Guide

3.7.3. Clock Details

Table 28.  Clock Signals for Design Examples with AXI4-stream Interface Enabled
Clock Signal Name Description
RX CDR Reference Clock

fgt_refclk_frl

fgt_refclk_tmds_rx

 Reference to the RX CDR. Reference clock 0 is connected to 100 Mhz for FRL. Reference clock 1 is connected to the RX TMDS clock from the HDMI sink connector
RX PHY Clock Out

rx_sysclk_div2

rx_clk

 Two output clocks from the RX transceiver. Refer to the Clocking Schemes table for details
RX FRL Clock rx_frl_clk FRL clock to the RX core. Refer to HDMI IP Core User Guide Section 5.5 FRL Clocking Scheme for the FRL clock frequency for each FRL rate
RX Video Clock rx_vid_clk Video clock to the RX core. The clock runs at a fixed frequency of 225 MHz
TX PLL Refclk

fgt_refclk_frl

fgt_refclk_tmds_tx

 Reference clock to the transceiver PLL. For FRL, this is a fixed 100 MHZ clock. For TMDS, the clock frequency follows the frequency of TMDS clock
TX PHY Clock Out

tx_sysclk_div2

tx_clk

 There are two output clocks from the TX transceiver. Refer to the Clocking Schemes table for details
TX FRL Clock tx_frl_clk FRL clock to the TX core. Refer to HDMI IP Core User Guide Section 5.5 FRL Clocking Scheme for the FRL clock frequency for each FRL rate
TX Video Clock tx_vid_clk Video clock to the RX core. In the RX-TX direct retransmit design without video frame buffer design, the clock runs at a fixed frequency of 225 MHz. In the RX-TX retransmit with video frame buffer design, the video clock is generated from a programmable oscillator at the frequency described in section Set TX Video Clock
Management Clock mgmt_clk

A free-running 100 MHz clock for these components:

  • IOPLL (Video Clock)
  • CPU
  • I2C master
  • HDMI TX/RX Core
  • RX-TX Link
System PLL Refclk systempll_clk Reference clock to the System PLL block. The clock only supports 100 MHz frequency
EMIF Refclk mem_pll_ref_clk Reference clock to External Memory Interface. This clock is 166.67 MHz in this design
Level Two Title