F-Tile HDMI Intel® FPGA IP Design Example User Guide

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ID 709314
Date 8/15/2023
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Document Table of Contents
Document Table of Contents x
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel Agilex® 7 F-tile Devices 2. HDMI 2.1 Design Example (Support FRL = 1, Enable Active Video Protocol = None) 3. HDMI 2.1 Design Example with AXI4-stream Interface Enabled (Support FRL =1, Enable Active Video Protocol = AXIS-VVP Full) 4. Document Revision History for the F-Tile HDMI Intel® FPGA IP Design Example User Guide
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel Agilex® 7 F-tile Devices x
1.1. Directory Structure 1.2. Generating the Design 1.3. Simulating the Design 1.4. Compiling and Testing the Design
2. HDMI 2.1 Design Example (Support FRL = 1, Enable Active Video Protocol = None) x
2.1. Design Features 2.2. Hardware and Software Requirements 2.3. HDMI 2.1 RX-TX Retransmit Design Block Diagram 2.4. Design Parameters 2.5. Design Components 2.6. Design Software Flow 2.7. Clocking Scheme 2.8. Interface Signals 2.9. Hardware Setup 2.10. Simulation Testbench 2.11. Debugging Features
2.3. HDMI 2.1 RX-TX Retransmit Design Block Diagram x
2.3.1. Creating RX-Only or TX-Only Designs
2.4. Design Parameters x
2.4.1. IP Parameters 2.4.2. HDMI Intel® FPGA IP Design Example Parameters
2.5. Design Components x
2.5.1. HDMI TX Components 2.5.2. HDMI RX Components 2.5.3. Top-Level Common Blocks
2.5.1. HDMI TX Components x
2.5.1.1. TX PHY Adapter
2.5.1.1. TX PHY Adapter x
2.5.1.1.1. FRL and TMDS
2.5.2. HDMI RX Components x
2.5.2.1. RX PHY Adapter
2.11. Debugging Features x
2.11.1. Software Debug Message 2.11.2. SCDC Information from Sink Connected to TX 2.11.3. Clock Frequency Measurement
3. HDMI 2.1 Design Example with AXI4-stream Interface Enabled (Support FRL =1, Enable Active Video Protocol = AXIS-VVP Full) x
3.1. Design Features 3.2. Hardware and Software Requirements 3.3. HDMI 2.1 RX-TX Retransmit Design Block Diagrams 3.4. Design Parameters 3.5. Design Components 3.6. Design Software Flow 3.7. Clocking Scheme 3.8. Interface Signals 3.9. Hardware Setup 3.10. Design Limitation (AXI/CV)
3.3. HDMI 2.1 RX-TX Retransmit Design Block Diagrams x
3.3.1. HDMI 2.1 RX-TX Direct Retransmit Design Block Diagram (Without Video Frame Buffer) 3.3.2. HDMI 2.1 RX-TX Retransmit Design Block Diagram (With Video Frame Buffer)
3.4. Design Parameters x
3.4.1. HDMI RX Direction 3.4.2. HDMI TX Direction
3.6. Design Software Flow x
3.6.1. Configure Redriver Setting 3.6.2. Initialize TX Path 3.6.3. Initialize RX Path 3.6.4. Initialize HDMI TX Register 3.6.5. Wait for RX Path Ready 3.6.6. TX Reconfiguration and Link Training 3.6.7. Set TX Video Clock 3.6.8. Set AXI2CV Configuration 3.6.9. HDMI TX Transmit Video
3.7. Clocking Scheme x
3.7.1. HDMI 2.1 RX-TX Retransmit Design without Video Frame Buffer (Enable Active Video Protocol = AXIS-VVP Full, Video In and Out Use the Same Clock = ON) 3.7.2. HDMI 2.1 RX-TX Retransmit Design with Video Frame Buffer (Enable Active Video Protocol = AXIS-VVP Full, Video In and Out Use the Same = OFF) 3.7.3. Clock Details
3.8. Interface Signals x
3.8.1. Platform Design System
3.9. Hardware Setup x
3.9.1. Supporting Additional Video Resolutions
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel Agilex® 7 F-tile Devices
2. HDMI 2.1 Design Example (Support FRL = 1, Enable Active Video Protocol = None)
3. HDMI 2.1 Design Example with AXI4-stream Interface Enabled (Support FRL =1, Enable Active Video Protocol = AXIS-VVP Full)
4. Document Revision History for the F-Tile HDMI Intel® FPGA IP Design Example User Guide

3.5. Design Components

Module Description
HDMI TX Core

The IP receives the video data in AXI4-stream format, auxiliary data and audio data and performs encoding, scrambling and packetization. With “enable active video protocol” parameter set to AXIS-VVP Full, the IP core expect incoming video data in AXI4-stream (full variant) format and HDMI control and status ports are accessible through Avalon memory-mapped interface.

In the HDMI RX-TX direct retransmit without video frame buffer design, video clock is driven by a fixed 225 MHz and Video in and out use the same clock is set to ON.

In the HDMI RX-TX retransmit with video frame buffer design, video clock is driven by a frequency equal to pixel rate or pixel in parallel. In this design, an external programmable oscillator is programmed to the desired video frequency above to drive the video clock. Video in and out use the same clock in the IP core is set to OFF

.
HDMI RX Core

The IP receives the recovered parallel data from the RX transceiver, performs data alignment, channel deskew, TMDS/FRL decoding, auxiliary data decoding, video data decoding, audio data decoding and descrambling.

With ”enable active video protocol” parameter set to AXIS-VVP Full, the IP core outputs the video data in AXI4-stream (full variant) format and enables access to HDMI control and status ports through Avalon® memory-mapped interface.

In both HDMI RX-TX retransmit with and without video frame buffer designs, video clock is driven by a fixed 225 MHz clock.
HDMI TX PHY

HDMI TX PHY receives the parallel data from the HDMI TX core and serializes the data to output the serial data to the four data lane on the HDMI TX connector.

HDMI TX PHY contains the TX transceiver, 80 to 128-bit data converter, DCFIFO, IOPLL to generate TX cadence clock, IOPLL to generate FRL clock, and TX reconfiguration management module.

Refer to section HDMI TX Components for details on each sub-blocks.

HDMI RX PHY

HDMI RX PHY receives the four or three serial data from the HDMI RX connector and deserializes the data into parallel data for the HDMI RX core.

HDMI RX PHY contains RX transceiver, DCFIFO, IOPLL to generate FRL clock, and RX reconfiguration module.

Refer to section HDMI RX Components for details on each sub-blocks.

F-tile Reference and System PLL Clock IP This block generates the reference clock to the transceiver TX PLL and transceiver RX CDR. This block also generates system clock to clock the data between transceiver and core fabrics
I2C Master (Redriver) An I2C master is used to tune the redriver setting through the Nios
I2C Master (TX clock) An I2C master is used to change the on-board programmable oscillator configuration to output the desired video clock frequency
FIFO A SCFIFO is used to retransmit auxiliary data and audio data from RX to TX
Dynamic Reconfig IP Dynamic reconfiguration IP is used to change TX and RX transceiver configurations to run at different FRL rate
Level Two Title