AN 961: IO Module Design Example for OPC UA: for Intel® MAX® 10 Devices

ID 691266
Date 10/30/2021
Public

Achieving Timing Closure on a Design Example

Intel® Quartus® Prime may not achieve full timing closure when it first compiles and fits this designs.

Intel® Quartus® Prime assume worst-case timing parameters over a wide range of temperature, which is good practice for a commercial design. If you run this design at room temperature, it is unlikely that real timing violations occur. To achieve full timing closure with Intel® Quartus® Prime, you may include additional pipeline registers. However, the place-and-route process is sensitive to an initial seed value and the result of different seeds is not easy to predict. Before optimizing the design, try the seed sweep function with many different seed values in case the design immediately fits.

  1. In Intel® Quartus® Prime, select Tools > Launch Design Space Explorer II.
    Design space Explorer opens in a separate window.
  2. For a basic seed sweep use the following settings:
    1. In Setup, select Local.
    2. In Exploration, select Design exploration, exploration mode: Seed Sweep Only, create 10 seeds.
    3. Click Start to run.
    4. Calculate the seed number from the exploration point name. It is the _number plus 1. In this example, the best seed is 3(dse1_3) + 1 = 4.
  3. Select Assignments > Settings.
  4. In complier settings, click Advanced settings (Fitter)….
  5. Update seed value Fitter Initial Placement Seed 4.